diff mbox series

[RFC,5/5] arm64: dts: qcom: ipq9574: Add support for SPI nand

Message ID 20231031120307.1600689-6-quic_mdalam@quicinc.com
State New
Headers show
Series Add QPIC SPI NAND driver support | expand

Commit Message

Md Sadre Alam Oct. 31, 2023, 12:03 p.m. UTC
Add support for QPIC SPI NAND for IPQ9574

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan R <quic_srichara@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 56 ++++++++++-----------
 arch/arm64/boot/dts/qcom/ipq9574.dtsi       | 30 ++++++++++-
 2 files changed, 57 insertions(+), 29 deletions(-)

Comments

Md Sadre Alam Nov. 3, 2023, 11:31 a.m. UTC | #1
On 10/31/2023 8:57 PM, Konrad Dybcio wrote:
> On 31.10.2023 13:03, Md Sadre Alam wrote:
>> Add support for QPIC SPI NAND for IPQ9574
>>
>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>> Signed-off-by: Sricharan R <quic_srichara@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 56 ++++++++++-----------
>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi       | 30 ++++++++++-
>>   2 files changed, 57 insertions(+), 29 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> index 1bb8d96c9a82..5e4200edb873 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> @@ -15,48 +15,48 @@ / {
>>   	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
>>   };
>>   
>> -&sdhc_1 {
>> -	pinctrl-0 = <&sdc_default_state>;
>> -	pinctrl-names = "default";
>> -	mmc-ddr-1_8v;
>> -	mmc-hs200-1_8v;
>> -	mmc-hs400-1_8v;
>> -	mmc-hs400-enhanced-strobe;
>> -	max-frequency = <384000000>;
>> -	bus-width = <8>;
>> -	status = "okay";
>> -};
> How is removing SDHCI related to adding support for SPI NAND flash?
> You must explain your changes in the commit message.
>


its my mistake will fix in V1

>> -
>>   &tlmm {
>> -	sdc_default_state: sdc-default-state {
>> -		clk-pins {
>> +	qspi_nand_pins: qspi_nand_pins {
> node names (between : and {) must not include underscores, use
> hyphens instead

ok

> 
>> +		spi_clock {
>>   			pins = "gpio5";
>> -			function = "sdc_clk";
>> +			function = "qspi_clk";
>>   			drive-strength = <8>;
>>   			bias-disable;
>>   		};
>>   
>> -		cmd-pins {
>> +		qspi_cs {
>>   			pins = "gpio4";
>> -			function = "sdc_cmd";
>> +			function = "qspi_cs";
>>   			drive-strength = <8>;
>>   			bias-pull-up;
>>   		};
>>   
>> -		data-pins {
>> -			pins = "gpio0", "gpio1", "gpio2",
>> -			       "gpio3", "gpio6", "gpio7",
>> -			       "gpio8", "gpio9";
>> -			function = "sdc_data";
>> +		qspi_data {
>> +			pins = "gpio0", "gpio1", "gpio2";
>> +			function = "qspi_data";
>>   			drive-strength = <8>;
>>   			bias-pull-up;
>>   		};
>>   
>> -		rclk-pins {
>> -			pins = "gpio10";
>> -			function = "sdc_rclk";
>> -			drive-strength = <8>;
>> -			bias-pull-down;
>> -		};
>> +	};
>> +};
>> +
>> +&qpic_bam {
>> +	status = "okay";
>> +};
>> +
>> +&qpic_nand {
>> +	status = "okay";
> status should come last
>> +	pinctrl-0 = <&qspi_nand_pins>;
>> +	pinctrl-names = "default";
>> +	spi_nand: spi_nand@0 {
> no underscores in node names
> missing newline between properties and subnodes

ok

> 
>> +		compatible = "spi-nand";
>> +		nand-ecc-engine = <&qpic_nand>;
>> +		reg = <0>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		nand-ecc-strength = <4>;
>> +		nand-ecc-step-size = <512>;
>> +		spi-max-frequency = <8000000>;
>>   	};
>>   };
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index b44acb1fac74..f9c21373f5e6 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -336,10 +336,38 @@ sdhc_1: mmc@7804000 {
>>   			status = "disabled";
>>   		};
>>   
>> +		qpic_bam: dma@7984000 {
>> +			compatible = "qcom,bam-v1.7.0";
>> +			reg = <0x7984000 0x1c000>;
>> +			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&gcc GCC_QPIC_AHB_CLK>;
>> +			clock-names = "bam_clk";
>> +			#dma-cells = <1>;
>> +			qcom,ee = <0>;
>> +			status = "disabled";
>> +		};
> You're modifying the SoC and board devicetrees in one go, this won't fly

Will fix in V1

> 
>> +
>> +		qpic_nand: spi@79b0000 {
>> +			compatible = "qcom,ipq9574-nand";
>> +			reg = <0x79b0000 0x10000>;
> 
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
> these two properties usually go below status, at the end

Ok

> 
>> +			clocks = <&gcc GCC_QPIC_CLK>,
>> +			<&gcc GCC_QPIC_AHB_CLK>,
>> +			<&gcc GCC_QPIC_IO_MACRO_CLK>;
> Indentation here is messy

Will fix in V1

> 
>> +			clock-names = "core", "aon", "io_macro";
> one per line, please
Ok
> 
>> +			dmas = <&qpic_bam 0>,
>> +				<&qpic_bam 1>,
>> +				<&qpic_bam 2>;
> ditto
Ok
> 
>> +			dma-names = "tx", "rx", "cmd";
> ditto
Ok
> 
>> +			nand-ecc-engine = <&bch>;
>> +			status = "disabled";
>> +		};
>> +
>>   		bch: qpic_ecc {
>>   			compatible = "qcom,ipq9574-ecc";
>>   			status = "ok";
>> -		}
>> +		};
> This means the previous dt patch would not compile

Will fix in V1


Regards
Alam.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
index 1bb8d96c9a82..5e4200edb873 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
@@ -15,48 +15,48 @@  / {
 	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
 };
 
-&sdhc_1 {
-	pinctrl-0 = <&sdc_default_state>;
-	pinctrl-names = "default";
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-	mmc-hs400-enhanced-strobe;
-	max-frequency = <384000000>;
-	bus-width = <8>;
-	status = "okay";
-};
-
 &tlmm {
-	sdc_default_state: sdc-default-state {
-		clk-pins {
+	qspi_nand_pins: qspi_nand_pins {
+		spi_clock {
 			pins = "gpio5";
-			function = "sdc_clk";
+			function = "qspi_clk";
 			drive-strength = <8>;
 			bias-disable;
 		};
 
-		cmd-pins {
+		qspi_cs {
 			pins = "gpio4";
-			function = "sdc_cmd";
+			function = "qspi_cs";
 			drive-strength = <8>;
 			bias-pull-up;
 		};
 
-		data-pins {
-			pins = "gpio0", "gpio1", "gpio2",
-			       "gpio3", "gpio6", "gpio7",
-			       "gpio8", "gpio9";
-			function = "sdc_data";
+		qspi_data {
+			pins = "gpio0", "gpio1", "gpio2";
+			function = "qspi_data";
 			drive-strength = <8>;
 			bias-pull-up;
 		};
 
-		rclk-pins {
-			pins = "gpio10";
-			function = "sdc_rclk";
-			drive-strength = <8>;
-			bias-pull-down;
-		};
+	};
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	status = "okay";
+	pinctrl-0 = <&qspi_nand_pins>;
+	pinctrl-names = "default";
+	spi_nand: spi_nand@0 {
+		compatible = "spi-nand";
+		nand-ecc-engine = <&qpic_nand>;
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		spi-max-frequency = <8000000>;
 	};
 };
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index b44acb1fac74..f9c21373f5e6 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -336,10 +336,38 @@  sdhc_1: mmc@7804000 {
 			status = "disabled";
 		};
 
+		qpic_bam: dma@7984000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x7984000 0x1c000>;
+			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_QPIC_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			status = "disabled";
+		};
+
+		qpic_nand: spi@79b0000 {
+			compatible = "qcom,ipq9574-nand";
+			reg = <0x79b0000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcc GCC_QPIC_CLK>,
+			<&gcc GCC_QPIC_AHB_CLK>,
+			<&gcc GCC_QPIC_IO_MACRO_CLK>;
+			clock-names = "core", "aon", "io_macro";
+			dmas = <&qpic_bam 0>,
+				<&qpic_bam 1>,
+				<&qpic_bam 2>;
+			dma-names = "tx", "rx", "cmd";
+			nand-ecc-engine = <&bch>;
+			status = "disabled";
+		};
+
 		bch: qpic_ecc {
 			compatible = "qcom,ipq9574-ecc";
 			status = "ok";
-		}
+		};
 
 		blsp_dma: dma-controller@7884000 {
 			compatible = "qcom,bam-v1.7.0";