| Message ID | 20240430142757.16872-3-quic_jkona@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for videocc and camcc on SM8650 | expand |
On 30/04/2024 15:27, Jagadeesh Kona wrote: > SM8650 video clock controller has most clocks same as SM8450, > but it also has few additional clocks and resets. Add device tree > bindings for the video clock controller on Qualcomm SM8650 platform > by defining these additional clocks and resets on top of SM8450. > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > --- > .../bindings/clock/qcom,sm8450-videocc.yaml | 6 ++++- > .../dt-bindings/clock/qcom,sm8650-videocc.h | 23 +++++++++++++++++++ > 2 files changed, 28 insertions(+), 1 deletion(-) > create mode 100644 include/dt-bindings/clock/qcom,sm8650-videocc.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > index 78a1bb5be878..922e95c61778 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > @@ -8,18 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450 > > maintainers: > - Taniya Das <quic_tdas@quicinc.com> > + - Jagadeesh Kona <quic_jkona@quicinc.com> > > description: | > Qualcomm video clock control module provides the clocks, resets and power > domains on SM8450. > > - See also:: include/dt-bindings/clock/qcom,sm8450-videocc.h > + See also:: > + include/dt-bindings/clock/qcom,sm8450-videocc.h > + include/dt-bindings/clock/qcom,sm8650-videocc.h > > properties: > compatible: > enum: > - qcom,sm8450-videocc > - qcom,sm8550-videocc > + - qcom,sm8650-videocc > > reg: > maxItems: 1 > diff --git a/include/dt-bindings/clock/qcom,sm8650-videocc.h b/include/dt-bindings/clock/qcom,sm8650-videocc.h > new file mode 100644 > index 000000000000..4e3c2d87280f > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,sm8650-videocc.h > @@ -0,0 +1,23 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H > +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H > + > +#include "qcom,sm8450-videocc.h" > + > +/* SM8650 introduces below new clocks and resets compared to SM8450 */ > + > +/* VIDEO_CC clocks */ > +#define VIDEO_CC_MVS0_SHIFT_CLK 12 > +#define VIDEO_CC_MVS0C_SHIFT_CLK 13 > +#define VIDEO_CC_MVS1_SHIFT_CLK 14 > +#define VIDEO_CC_MVS1C_SHIFT_CLK 15 > +#define VIDEO_CC_XO_CLK_SRC 16 > + > +/* VIDEO_CC resets */ > +#define VIDEO_CC_XO_CLK_ARES 7 > + > +#endif Extensibility +1 Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
On 30/04/2024 16:27, Jagadeesh Kona wrote: > SM8650 video clock controller has most clocks same as SM8450, > but it also has few additional clocks and resets. Add device tree > bindings for the video clock controller on Qualcomm SM8650 platform > by defining these additional clocks and resets on top of SM8450. > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 78a1bb5be878..922e95c61778 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -8,18 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450 maintainers: - Taniya Das <quic_tdas@quicinc.com> + - Jagadeesh Kona <quic_jkona@quicinc.com> description: | Qualcomm video clock control module provides the clocks, resets and power domains on SM8450. - See also:: include/dt-bindings/clock/qcom,sm8450-videocc.h + See also:: + include/dt-bindings/clock/qcom,sm8450-videocc.h + include/dt-bindings/clock/qcom,sm8650-videocc.h properties: compatible: enum: - qcom,sm8450-videocc - qcom,sm8550-videocc + - qcom,sm8650-videocc reg: maxItems: 1 diff --git a/include/dt-bindings/clock/qcom,sm8650-videocc.h b/include/dt-bindings/clock/qcom,sm8650-videocc.h new file mode 100644 index 000000000000..4e3c2d87280f --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8650-videocc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H + +#include "qcom,sm8450-videocc.h" + +/* SM8650 introduces below new clocks and resets compared to SM8450 */ + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_SHIFT_CLK 12 +#define VIDEO_CC_MVS0C_SHIFT_CLK 13 +#define VIDEO_CC_MVS1_SHIFT_CLK 14 +#define VIDEO_CC_MVS1C_SHIFT_CLK 15 +#define VIDEO_CC_XO_CLK_SRC 16 + +/* VIDEO_CC resets */ +#define VIDEO_CC_XO_CLK_ARES 7 + +#endif
SM8650 video clock controller has most clocks same as SM8450, but it also has few additional clocks and resets. Add device tree bindings for the video clock controller on Qualcomm SM8650 platform by defining these additional clocks and resets on top of SM8450. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> --- .../bindings/clock/qcom,sm8450-videocc.yaml | 6 ++++- .../dt-bindings/clock/qcom,sm8650-videocc.h | 23 +++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,sm8650-videocc.h