| Message ID | 20240517-i2c-th1520-v2-2-d364d135ccc6@bootlin.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add I2C support on TH1520 | expand |
Hi Thomas, Thanks for the patch. Some comments below. Thomas Bonnefille wrote: > Add nodes for the five I2C on the T-Head TH1520 RISCV SoC. > > Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> > --- > arch/riscv/boot/dts/thead/th1520.dtsi | 50 +++++++++++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > index de7116290ca4..ae6cf4c441cf 100644 > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > @@ -252,6 +252,36 @@ gpio2: gpio-controller@0 { > }; > }; > > + i2c0: i2c@ffe7f20000 { > + compatible = "thead,th1520-i2c", "snps,designware-i2c"; > + reg = <0xff 0xe7f20000 0x0 0x4000>; > + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk CLK_I2C0>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c1: i2c@ffe7f24000 { > + compatible = "thead,th1520-i2c", "snps,designware-i2c"; > + reg = <0xff 0xe7f24000 0x0 0x4000>; > + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk CLK_I2C1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c4: i2c@ffe7f28000 { > + compatible = "thead,th1520-i2c", "snps,designware-i2c"; > + reg = <0xff 0xe7f28000 0x0 0x4000>; > + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk CLK_I2C4>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + These nodes should be ordered by their memory addres, but the gpio2 controller above has address 0xffe7f34000 which is greater than i2c0 at 0xffe7f20000. > gpio@ffe7f38000 { > compatible = "snps,dw-apb-gpio"; > reg = <0xff 0xe7f38000 0x0 0x1000>; > @@ -342,6 +372,16 @@ uart2: serial@ffec010000 { > status = "disabled"; > }; > > + i2c3: i2c@ffec014000 { > + compatible = "thead,th1520-i2c", "snps,designware-i2c"; > + reg = <0xff 0xec014000 0x0 0x4000>; > + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk CLK_I2C3>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > dmac0: dma-controller@ffefc00000 { > compatible = "snps,axi-dma-1.01a"; > reg = <0xff 0xefc00000 0x0 0x1000>; > @@ -416,6 +456,16 @@ uart5: serial@fff7f0c000 { > status = "disabled"; > }; > > + i2c5: i2c@fff7f2c000 { > + compatible = "thead,th1520-i2c", "snps,designware-i2c"; > + reg = <0xff 0xf7f2c000 0x0 0x4000>; > + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk CLK_I2C5>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + I know it's probably hard to test i2c2 with the Ahead board, but chances are very low that the disignware driver works with i2c0, i2c1, i2c3, i2c4 and i2c5, but not i2c2, so plaese add that node too. The audio and aon i2cs are fine to add later. > timer4: timer@ffffc33000 { > compatible = "snps,dw-apb-timer"; > reg = <0xff 0xffc33000 0x0 0x14>; > > -- > 2.45.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index de7116290ca4..ae6cf4c441cf 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -252,6 +252,36 @@ gpio2: gpio-controller@0 { }; }; + i2c0: i2c@ffe7f20000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f20000 0x0 0x4000>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@ffe7f24000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f24000 0x0 0x4000>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ffe7f28000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f28000 0x0 0x4000>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpio@ffe7f38000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f38000 0x0 0x1000>; @@ -342,6 +372,16 @@ uart2: serial@ffec010000 { status = "disabled"; }; + i2c3: i2c@ffec014000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xec014000 0x0 0x4000>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dmac0: dma-controller@ffefc00000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xefc00000 0x0 0x1000>; @@ -416,6 +456,16 @@ uart5: serial@fff7f0c000 { status = "disabled"; }; + i2c5: i2c@fff7f2c000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xf7f2c000 0x0 0x4000>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer4: timer@ffffc33000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33000 0x0 0x14>;
Add nodes for the five I2C on the T-Head TH1520 RISCV SoC. Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> --- arch/riscv/boot/dts/thead/th1520.dtsi | 50 +++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)