From patchwork Mon Nov 6 13:27:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 741395 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1083792wrr; Mon, 6 Nov 2023 05:27:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IHbuL85flrXB0k6HGKd4OyzI85ePfE+Nu5CQaS/k4b8vU0EvfCCHXscYJU8Zz1+4eTOXch0 X-Received: by 2002:ac8:5d06:0:b0:41b:7759:2a9a with SMTP id f6-20020ac85d06000000b0041b77592a9amr39074169qtx.13.1699277274514; Mon, 06 Nov 2023 05:27:54 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1699277274; cv=pass; d=google.com; s=arc-20160816; b=lBUJFmDpsEs/7Y7EzAkrSlFdhcYINlqZyzL5pZ7+3OAOR8GMwqdS9/3sdo5Lgh90L8 2m9Ot2xMGudS9TYe3vaKJPEhlvhFTNCMcm293H3wUS8HUiZHlq/QqkLpAvEmA0zI9zUg QZjIWNfjYDBQfwKudqCwdbscWCw/rmJwUfFZfX43ZqRQIH9Jb1M02gED0D2fmA7x0onr g6PtpIAuILkkgw4qVRgaWZQ1s/mWnv/LQr3zsWsXUgG7/waYRiIqKScUxMg8Bys+CYUk hZlHWwx52bGgbA2nTmzVdnJhI+TCIHQF09UApB2QIWS67f7QV0wtEknnzeutiLZT2n4t fA6g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=OsJVfrzuJQEStROxTkYGHeK2o8XwhP+5e/BtTCdJZcc=; fh=01HD8dtuIqmy9rV/eMJuvD8dAGq4TXBqBjIxWaMzNQI=; b=tEV0vTY99z6JCPZhtJUhNd00tQfNZZO8GJnhFMZYJWpy4FKIb+zpSClg5n6zKqk1++ DV7hOeTwKSvGA5INeEDxrN0TG5wCxd+WZZdjJL1dKkp77rmhPX0cb7bKiiKGvkM9qKnC M9/gW0oft7N04Eh1kBnUNyvy407Ng4JsqClEQ+ljOd10yqhRQXZv4T2AhBQUi1zbx0te 7MevcIex2bv1W6Haw/HMv65JOjb98sTPI/mZDPtdBLhMsAjWLl0Msf79p19UjJU/8Jlb wlMyYMgfe4ob/lihvWLQlZY946/Am5m+2GvATStaabDsR/GQUEdj8byK0U0GNMFwjgBV anfQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VxFuMLfb; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id v4-20020ac85784000000b0041b827563f0si5742970qta.331.2023.11.06.05.27.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:54 -0800 (PST) Received-SPF: pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VxFuMLfb; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 323EF3861880 for ; Mon, 6 Nov 2023 13:27:54 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by sourceware.org (Postfix) with ESMTPS id E94763857726 for ; Mon, 6 Nov 2023 13:27:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E94763857726 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E94763857726 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::730 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699277246; cv=none; b=mSlciq3SLxUc1bCPPqEawnyJ/X4PN7b9JFvQFuunhv1RhoPKjbqO62zLjiMe9E5/SGTlCsqd4/BxshyPi1syy2oUoB7uSMBM6X0Nreylt6OlnVnazrbxkYjMrh8WseMcxDkwkkQzUAmw2iCH3k8Ty9wIyDAoyWp6gvku+a3BJbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699277246; c=relaxed/simple; bh=Ow8ezhxiuH9AjJBrNW3xl/fniSBKhwkM4WQInFo1muo=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=I3Mfvz6bJqE0RwZZnQJEHY9fK9+MUN8mEqeWa7Y7OoBOZOVo4jVhUtqlaYCs4wMjllscMx11wQ4fPzMC8OsmPpXj89Ni2P0dTttgBVu0UTCDooFDyMSleAn4Z1sD26i3jL+LtV14xHMqI4tzhJ9OcxAhInEUI/KjVywe2aHjoyE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-qk1-x730.google.com with SMTP id af79cd13be357-778999c5ecfso290302685a.2 for ; Mon, 06 Nov 2023 05:27:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699277243; x=1699882043; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OsJVfrzuJQEStROxTkYGHeK2o8XwhP+5e/BtTCdJZcc=; b=VxFuMLfboO9/gl1SXjaPlkFBYmsgT8jPE02UpnX7zjQjMqlG616/R7YotBiRpM81Rb GiFqeiNNFMfGT7+ksfPySOk0rpnQ93Wkuyb9m/owUI15+YoYciP/GIiHUa1c3AmDhd/U jGhGiJ5E2wBicJ2CwpOP/e5ftQQGUt3CQ7x296OfZ1fKQOn9bZtsO8PETohkB7fstrWO 4XsBeH/MLdfJW/Zpgep97W+gElQ7yP6IwZU+Z+4LhU58uk5j1S+LT4Te/8Q/mbD3lz+r qLC+n4cUz+s8ERFkYBsibv6F/vRcbTySPMUyCDceNzl5EiNvxSryGB+nnumAV+BDFLo6 WbXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699277243; x=1699882043; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OsJVfrzuJQEStROxTkYGHeK2o8XwhP+5e/BtTCdJZcc=; b=a3LvV6w4fP0tjIwBzL8MxOSa5WEKvzjyJMD5jrFF7SaR9WfY39tYjPxHN11XNj2Gnv qiFztrQwH0Ty/oFmejMr55tGHnLvdJSaMIPhZGePnKW+toveNNNw7lZUkwo9SJ8FBUuW UZx2R534fM2IjMhZcn+Pct72/tiRKbeufSoUE3PH01DlZBtZGYW/J910ZvOmiXMckUIu eFoe8CcIdI33Oh5MVuPGEyJhNN5horL8PbGPMBl+SMElZ2onONkyeBVzirJWATJxADxY 7uD35MMJLtyW1evaeyOo3mHxA41n9YCY3q5Bei4+eZQTP8rJNWm2xj8PbDndtwiArDKe xHwg== X-Gm-Message-State: AOJu0YzO9i0JLsY+sbri3yL6x/fsPOv6Z5yim3k9MhddnDFkIn8CR1dd 0O4WCeR8HWN/Ir5DrS4UlSf9fAxGnGFM9bxS3KbyTw== X-Received: by 2002:a05:620a:2890:b0:77a:2de5:2cf0 with SMTP id j16-20020a05620a289000b0077a2de52cf0mr24735193qkp.11.1699277243409; Mon, 06 Nov 2023 05:27:23 -0800 (PST) Received: from mandiga.. ([2804:1b3:a7c0:a715:c1a0:7281:6384:2ee9]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a142300b0076f12fcb0easm3272722qkj.2.2023.11.06.05.27.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 05:27:22 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH v2 3/7] x86: Do not raises floating-point exception traps on fesetexceptflag (BZ 30990) Date: Mon, 6 Nov 2023 10:27:09 -0300 Message-Id: <20231106132713.953501-4-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106132713.953501-1-adhemerval.zanella@linaro.org> References: <20231106132713.953501-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. When we need to clear a flag, we need to do so in both units, due to the way fetestexcept is implemented. When we need to set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Co-authored-by: Adhemerval Zanella Reviewed-by: Carlos O'Donell --- math/test-fexcept-traps.c | 25 +++++++++++- sysdeps/i386/fpu/fsetexcptflg.c | 63 ++++++++++++++++++++----------- sysdeps/x86_64/fpu/fsetexcptflg.c | 24 +++++++----- 3 files changed, 79 insertions(+), 33 deletions(-) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9b8f583ae6..6bfb5124da 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -65,8 +66,28 @@ do_test (void) /* The test is that this does not cause exception traps. For architectures where setting the exception might result in traps the function should - return a nonzero value. */ - ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + return a nonzero value. + Also check if the function does not alter the exception mask. */ + { + int exc_before = fegetexcept (); + ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + int exc_after = fegetexcept (); + if (exc_before != exc_after) + { + puts ("fesetexceptflag (FE_ALL_EXCEPT) changed the exceptions mask"); + return 1; + } + } + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + volatile double a = 1.0; + volatile double b = a + a; + math_force_eval (b); + volatile long double al = 1.0L; + volatile long double bl = al + al; + math_force_eval (bl); + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); diff --git a/sysdeps/i386/fpu/fsetexcptflg.c b/sysdeps/i386/fpu/fsetexcptflg.c index e724b7d6fd..480165cff9 100644 --- a/sysdeps/i386/fpu/fsetexcptflg.c +++ b/sysdeps/i386/fpu/fsetexcptflg.c @@ -17,42 +17,63 @@ . */ #include -#include -#include #include -#include int __fesetexceptflag (const fexcept_t *flagp, int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. When we need to + clear a flag, we need to do so in both units, due to the way fetestexcept + is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. However, on i386 CPUs that have + only a 387 unit, set the flags in the 387, as long as this cannot trap. */ - /* Get the current environment. We have to do this since we cannot - separately set the status word. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); + fenv_t temp; - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + excepts &= FE_ALL_EXCEPT; - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ - __asm__ ("fldenv %0" : : "m" (*&temp)); + /* Get the current x87 FPU environment. We have to do this since we + cannot separately set the status word. + Note: fnstenv masks all floating-point exceptions until the fldenv + or fldcw below. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); - /* If the CPU supports SSE, we set the MXCSR as well. */ if (CPU_FEATURE_USABLE (SSE)) { - unsigned int xnew_exc; + unsigned int mxcsr; + + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Get the current MXCSR. */ - __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc)); + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); - /* Set the relevant bits. */ - xnew_exc &= ~(excepts & FE_ALL_EXCEPT); - xnew_exc |= *flagp & excepts & FE_ALL_EXCEPT; + /* And now similarly for SSE. */ + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; /* Put the new data in effect. */ - __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc)); + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + /* Clear or set relevant flags. */ + temp.__status_word ^= (temp.__status_word ^ *flagp) & excepts; + + if ((~temp.__control_word) & temp.__status_word & excepts) + { + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C 23 ยง 7.6.4.5 does not allow it. */ + __asm__ volatile ("fldcw %0" : : "m" (*&temp.__control_word)); + return -1; + } + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); } /* Success. */ diff --git a/sysdeps/x86_64/fpu/fsetexcptflg.c b/sysdeps/x86_64/fpu/fsetexcptflg.c index a3ac1dea01..2ce2b509f2 100644 --- a/sysdeps/x86_64/fpu/fsetexcptflg.c +++ b/sysdeps/x86_64/fpu/fsetexcptflg.c @@ -22,30 +22,34 @@ int fesetexceptflag (const fexcept_t *flagp, int excepts) { + /* The flags can be set in the 387 unit or in the SSE unit. + When we need to clear a flag, we need to do so in both units, + due to the way fetestexcept() is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. */ + fenv_t temp; unsigned int mxcsr; - /* XXX: Do we really need to set both the exception in both units? - Shouldn't it be enough to set only the SSE unit? */ + excepts &= FE_ALL_EXCEPT; /* Get the current x87 FPU environment. We have to do this since we cannot separately set the status word. */ __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ + /* Store the new status word (along with the rest of the environment). */ __asm__ ("fldenv %0" : : "m" (*&temp)); - /* And now the same for SSE. */ + /* And now similarly for SSE. */ __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); - mxcsr &= ~(excepts & FE_ALL_EXCEPT); - mxcsr |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; + /* Put the new data in effect. */ __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); /* Success. */