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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id p8-20020a5d48c8000000b0034af40b2efdsm23595951wrs.108.2024.04.30.03.44.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 03:44:18 -0700 (PDT) From: Connor Abbott Date: Tue, 30 Apr 2024 11:43:20 +0100 Subject: [PATCH v3 6/6] drm/msm/a7xx: Add missing register writes from downstream Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-a750-raytracing-v3-6-7f57c5ac082d@gmail.com> References: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> In-Reply-To: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714473850; l=1178; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=jmofaJ3QWKGh4FuQgnidJQUjJ4vAccqiIwWwk4VBoUk=; b=ujp5kRgQelCyVGrPXqO7Kl6H4xLU3dtkkFWc1xAKk6SPvxdAcmD/lCjWErIW2i2gG1Q8n+eOT XvDBjRqaVWmBj97gf7s7X4XErXC6is+dMOqDznpv0NP0SF0YmjR4s+R X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= This isn't known to fix anything yet, but it's a good idea to add it. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 52b080206090..24a4ed9bfea9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1953,6 +1953,17 @@ static int hw_init(struct msm_gpu *gpu) BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); } + if (adreno_is_a750(adreno_gpu)) { + /* Disable ubwc merged UFC request feature */ + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); + + /* Enable TP flaghint and other performance settings */ + gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); + } else if (adreno_is_a7xx(adreno_gpu)) { + /* Disable non-ubwc read reqs from passing write reqs */ + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(11), BIT(11)); + } + /* Enable interrupts */ gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK);