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AJvYcCVk30N1krhWCXfZRAlRgsJ1A4XGlscIh+L8tuK2bxrpEIQE66lUFp7tY0M7a3Swgzy/C/Ytv8J1xbAd1LDLGb0C4y9x0HwwrL7S96yWVwM5IZ2JahpyYYjib3vOP94gtzispiqjdxnI8ZBs+dZ2DYNNhJZqV4yegn/fcG4RnrxP2wk3gJOAVIb3Ueqf X-Gm-Message-State: AOJu0YwuxpnYxAt7jr8SXyuD+5d8EheJJuS0c3ndQGm/6s5WO090tm90 JWlcYes/cCwkAnVcFfBuPTSJCnwQxZuWUef2reprhCCibNBcWPpX X-Google-Smtp-Source: AGHT+IH5buIEi/VPw6QAuTpTWyRW4A+k0YzEFzIQb6LtOXv4k1FqZjEkPD71f3r/9FJjqYZEXaGtjg== X-Received: by 2002:a05:600c:3590:b0:41a:93f3:5c6b with SMTP id p16-20020a05600c359000b0041a93f35c6bmr29752wmq.11.1713895160952; Tue, 23 Apr 2024 10:59:20 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:cef0:9ed3:1428:f85f]) by smtp.gmail.com with ESMTPSA id fl5-20020a05600c0b8500b0041abeaaf7f0sm2808145wmb.28.2024.04.23.10.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Apr 2024 10:59:20 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-renesas-soc@vger.kernel.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 05/13] pinctrl: renesas: pinctrl-rzg2l: Validate power registers for SD and ETH Date: Tue, 23 Apr 2024 18:58:52 +0100 Message-Id: <20240423175900.702640-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240423175900.702640-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240423175900.702640-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist, resulting in invalid register offsets. Ensure that the register offsets are valid before any read/write operations are performed. If the power registers are not available, both SD and ETH will be set to '0'. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- RFC->v2 - Update check to != 0 instead of -EINVAL --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index c944d94b9a36..bec4685b4681 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2583,8 +2583,10 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev) rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); for (u8 i = 0; i < 2; i++) { - cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); - cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); + if (regs->sd_ch) + cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); + if (regs->eth_poc) + cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); } cache->qspi = readb(pctrl->base + QSPI); @@ -2615,8 +2617,10 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) writeb(cache->qspi, pctrl->base + QSPI); writeb(cache->eth_mode, pctrl->base + ETH_MODE); for (u8 i = 0; i < 2; i++) { - writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); - writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); + if (regs->sd_ch) + writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); + if (regs->eth_poc) + writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); } rzg2l_pinctrl_pm_setup_pfc(pctrl);