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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id dk21-20020a170907941500b00a55aee4bf74sm9976074ejc.79.2024.04.29.06.02.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 06:02:30 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 29 Apr 2024 14:02:18 +0100 Subject: [PATCH v3 2/3] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240429-hsi0-gs101-v3-2-f233be0a2455@linaro.org> References: <20240429-hsi0-gs101-v3-0-f233be0a2455@linaro.org> In-Reply-To: <20240429-hsi0-gs101-v3-0-f233be0a2455@linaro.org> To: Peter Griffin , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi Cc: Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.12.4 From: Peter Griffin Enable the cmu_hsi2 clock management unit. It feeds some of the high speed interfaces such as PCIe and UFS. Signed-off-by: Peter Griffin Reviewed-by: Tudor Ambarus Signed-off-by: André Draszik --- v3: * s/ufs_embd/ufs * s/mmc_card/mmc --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9755a0bb70a1..a0305555c4fd 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1267,6 +1267,18 @@ pinctrl_hsi1: pinctrl@11840000 { interrupts = ; }; + cmu_hsi2: clock-controller@14400000 { + compatible = "google,gs101-cmu-hsi2"; + reg = <0x14400000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; + clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>;