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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id a7-20020a170906670700b00a522bef9f06sm13717707ejp.181.2024.04.29.03.35.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 03:35:51 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 29 Apr 2024 11:35:49 +0100 Subject: [PATCH v2 1/2] arm64: dts: exynos: gs101: add USB & USB-phy nodes Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240429-usb-dts-gs101-v2-1-7c1797c9db80@linaro.org> References: <20240429-usb-dts-gs101-v2-0-7c1797c9db80@linaro.org> In-Reply-To: <20240429-usb-dts-gs101-v2-0-7c1797c9db80@linaro.org> To: Peter Griffin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Tudor Ambarus , Will McVicker , Roy Luo , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.12.4 Add the USB 3.1 Dual Role Device (DRD) controller and USB-PHY nodes for Google Tensor GS101. The USB 3.1 DRD controller has the following features: * compliant with both USB device 3.1 and USB device 2.0 standards * compliant with USB host 3.1 and USB host 2.0 standards * supports USB device 3.1 and USB device 2.0 interfaces * supports USB host 3.1 and USB host 2.0 interfaces * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface * single USB port which can be used for USB 3.1 or USB 2.0 * on-chip USB PHY transceiver * DWC3 compatible * supports up to 16 bi-directional endpoints * compliant with xHCI 1.1 specification Signed-off-by: André Draszik --- v2: fix commit message --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9755a0bb70a1..217699477b32 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1261,6 +1261,47 @@ cmu_hsi0: clock-controller@11000000 { "usbdpdbg"; }; + usbdrd31_phy: phy@11100000 { + compatible = "google,gs101-usb31drd-phy"; + reg = <0x11100000 0x0100>, + <0x110f0000 0x0800>, + <0x110e0000 0x2800>; + reg-names = "phy", "pcs", "pma"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; + clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + status = "disabled"; + }; + + usbdrd31: usb@11110000 { + compatible = "google,gs101-dwusb3"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; + clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x11110000 0x10000>; + status = "disabled"; + + usbdrd31_dwc3: usb@0 { + compatible = "snps,dwc3"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; + clock-names = "ref"; + reg = <0x0 0x10000>; + interrupts = ; + phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + }; + pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>;