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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CEA.mail.protection.outlook.com (10.167.242.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7519.19 via Frontend Transport; Thu, 25 Apr 2024 06:24:37 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 25 Apr 2024 01:24:35 -0500 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 25 Apr 2024 01:24:29 -0500 From: Manikanta Guntupalli To: , , , , , , , , , , , , , , , , , , CC: , , , Manikanta Guntupalli Subject: [PATCH V3 3/3] tty: serial: uartps: Add support for uartps controller reset Date: Thu, 25 Apr 2024 11:53:58 +0530 Message-ID: <20240425062358.1347684-4-manikanta.guntupalli@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240425062358.1347684-1-manikanta.guntupalli@amd.com> References: <20240425062358.1347684-1-manikanta.guntupalli@amd.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: manikanta.guntupalli@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|CH3PR12MB8934:EE_ X-MS-Office365-Filtering-Correlation-Id: 14d94d5d-189f-4ff8-d28e-08dc64f061bc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 35BXcfmY9dWjAlXa5gB6Y44RBeDixyReRcHYAEk7i+wtA5xzy34HV1kDubbZ5siG5Shusgz9cfr4xDOnWIysR6yNW9emLq5gDJ3nHAzM7FZ2sXy4K718eLNuKJsGEgJlI/sGzOawpQAwEjrvfvmrKJBHbkdIHhtiZ5KZfFxh/oqbVr3dKNmrxbEPH0pLnCxkhtaIu+bOvXqwMGIN5AiBDuG0YsgaCuH66uCyWNs51A55V8ypO5p3aaR61PhwvVzkLk7+CksQKwZvZ0HSmnuuyQrpbQxlC8/FrFuQ/+qcPkSYrvr0Ye+v+J/f5mrBxB+mRud3PcRlrTi5sbLjVutPSI4E9ljOOw4SWIwy/PXedEn7+zMpLP+ngOE45DYuCXG4Gk/MYlK824CFRp4T/xAeywJ/OA6NSj1HGO3jjnfSiY0nL6llSh31V8YFZ7jVofsD805nR2NUn/Wxm7Le7b+4WWm/YGKnmAxhqOZUdL6WQJpggoZRR5sFRmGr2WWUuMP72afEQG/7w9mJyt6/ebPfQQq6YMyyYeFE6WTqMS59eM5k0lTbZgD9lJ94X6A2VsI/cClCRPOhtFNyEa5aL9U/DOqSKSzEVm2zzZWAiVuT4ck0uQ6rz+nwaLbjfB7CZyEnpuBJs/+ZHADjCv5wPOZRLtVNL0mmTDznU2JEOIMSqgXL4pzetyOx9Ub2zKBupdxgmUFB+xknIINJxl9AvpjEKs68VycqamS9Nt+635jqw5w97rnofNEm09mEFKDjHIWSfYaZt/Zmf8zIo9kox1ayRAISFrCUZer0VsEibugfoFLeERUdvsQJiHZZSBA2BBxrqxwA3mdZ6iHdOYjFUitlj/HOFc/RFwULwekL4J3KFixEjolE8JwepELyzrRi7oFx4FEtgOUP1yEaG9NlTIWDk/UlLReGb/zpIRJgidgQuFQSwlJmeWWITQyd7lGek4Z0tq8cbRhPONsrl0pMUeWuM2o88eD75ryIoWNqVyicjyKI3CQp9EnuOyZXakS2eCE+FNJkGa7UefPatFmgr1hK8B7zx3e9ypqhasfCFj27Hv5h9SFs9x1v9wV5pLLXYLbRnsO9M7S0L+8813Imvo/gOYZ/SD1lfzh+TSXPOPaAK6IaxPDSA78ybdyMjP9ODG8U/mZyLPndoIY98yeLj2e6gn/ghhTeTkBjQZGPOfmihrEfoTmPOrAO7KTwh9ifd9/xBwc0xyYGJC+hlW25otQ2SG4Z1Mkwu4V/Y7qU6OoEjeBK2RqP51TBaG9Bs9BT0dhhoVrCmXfdDzZEwmCH742ktXsuAmGxBzRyn1nzjBum6zTk2h0j2wteiVIpt8Zf45o19bjxIPWGFUZxg6COOFjrHlDYZOEzg1F8BXEv3NMQA2lXjwzOertC4IkpvV7jSU1g X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(82310400014)(1800799015)(376005)(36860700004)(7416005)(921011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2024 06:24:37.3211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14d94d5d-189f-4ff8-d28e-08dc64f061bc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8934 Add support for an optional reset for the uartps controller using the reset driver. If the uartps node contains the "resets" property, then cdns_uart_startup performs uartps controller non-pulse out of reset and reset in exit path. Signed-off-by: Manikanta Guntupalli --- Changes for V2: Remove check for reset_control_deassert, as reset_control_deassert function internally has NULL check. Changes for V3: None. --- drivers/tty/serial/xilinx_uartps.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c index de3487206bcb..2acfcea403ce 100644 --- a/drivers/tty/serial/xilinx_uartps.c +++ b/drivers/tty/serial/xilinx_uartps.c @@ -25,6 +25,7 @@ #include #include #include +#include #define CDNS_UART_TTY_NAME "ttyPS" #define CDNS_UART_NAME "xuartps" @@ -198,6 +199,7 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); * @gpiod_rts: Pointer to the gpio descriptor * @rs485_tx_started: RS485 tx state * @tx_timer: Timer for tx + * @rstc: Pointer to the reset control */ struct cdns_uart { struct uart_port *port; @@ -211,6 +213,7 @@ struct cdns_uart { struct gpio_desc *gpiod_rts; bool rs485_tx_started; struct hrtimer tx_timer; + struct reset_control *rstc; }; struct cdns_platform_data { u32 quirks; @@ -948,6 +951,10 @@ static int cdns_uart_startup(struct uart_port *port) is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; + ret = reset_control_deassert(cdns_uart->rstc); + if (ret) + return ret; + uart_port_lock_irqsave(port, &flags); /* Disable the TX and RX */ @@ -1721,6 +1728,13 @@ static int cdns_uart_probe(struct platform_device *pdev) dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); } + cdns_uart_data->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); + if (IS_ERR(cdns_uart_data->rstc)) { + rc = PTR_ERR(cdns_uart_data->rstc); + dev_err_probe(&pdev->dev, rc, "Cannot get UART reset\n"); + goto err_out_unregister_driver; + } + rc = clk_prepare_enable(cdns_uart_data->pclk); if (rc) { dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); @@ -1881,6 +1895,7 @@ static void cdns_uart_remove(struct platform_device *pdev) if (console_port == port) console_port = NULL; #endif + reset_control_assert(cdns_uart_data->rstc); if (!--instances) uart_unregister_driver(cdns_uart_data->cdns_uart_driver);