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[206.45.179.115]) by smtp.gmail.com with ESMTPSA id f5-20020a056638112500b003495b85a3b9sm4004995jar.178.2022.09.12.10.05.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 10:05:18 -0700 (PDT) From: jassisinghbrar@gmail.com To: trini@konsulko.com, u-boot@lists.denx.de Cc: kojima.masahisa@socionext.com, ilias.apalodimas@linaro.org, Jassi Brar Subject: [PATCH 1/2] board: developerbox: use identity mapping for >4GB Date: Mon, 12 Sep 2022 12:05:15 -0500 Message-Id: <20220912170515.718989-1-jassisinghbrar@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Jassi Brar Identity-map the second and later memory banks which are located >4GB. Signed-off-by: Jassi Brar --- board/socionext/developerbox/developerbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 9552bfcdc3..b680f77d80 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -127,11 +127,11 @@ int dram_init(void) ri = DDR_REGION_INDEX(i); mem_map[ri].phys = ent[i].base; mem_map[ri].size = ent[i].size; + mem_map[ri].virt = mem_map[ri].phys; if (i == 0) continue; mr = &mem_map[DDR_REGION_INDEX(0)]; - mem_map[ri].virt = mr->virt + mr->size; mem_map[ri].attrs = mr->attrs; } From patchwork Mon Sep 12 17:05:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jassi Brar X-Patchwork-Id: 604991 Delivered-To: patch@linaro.org Received: by 2002:a05:6504:2213:b0:1da:4c02:b5e7 with SMTP id z19csp2732170ltw; Mon, 12 Sep 2022 10:05:41 -0700 (PDT) X-Google-Smtp-Source: AA6agR4dJe+diDIZ4StWgMByVzyyhO9Bs3XDTS0b9oit7NfoDYAp2EcsALsTEOpiId5O2J+3LMTP X-Received: by 2002:a17:907:7621:b0:741:6656:bd14 with SMTP id jy1-20020a170907762100b007416656bd14mr18829712ejc.298.1663002341486; Mon, 12 Sep 2022 10:05:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663002341; cv=none; d=google.com; s=arc-20160816; b=u++uDp48Nifol7CWeTjMJVMIHQ+uxisGBcLhwWlKQEOkYNqCVqesKfYZJW1C7jdh81 WIp5/72qRiyzCSmhVwwqjy8C+n3lpngBHPQvvKh8Wwob0D/DBaM9BO0q9oXhl9/aLGjD BcSTV9Jh572bNrUbrckLNjUoFVgJNuc7S6TRLjSx883yh+bAdsaOz9ibB+2HXdC8MvOc Bw6aOvv8QXEdEcV/A9MwxQWilXu3maBkzf/9ZKjs7orcJJbCxOX4Mj51iEc7oNt/3Qeb Vpqj+bCN5F412ma2kjqNaxtBmqwqpLTfTkIkkerwl4fL0IyIIC8UT0jMwRVs7qwWEFLN rP/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature; bh=o91WJ0rjG0Wpot+iXXdGthvZyC5h2f8E3lxv7FocqJM=; b=Ld5/i7wlbBxN3VWbyLsNCBeuHIoRJ3xzHELpd7T8MZ7OXiOoQnz9mHSuaYiSXoh6T5 jDihWXcsAV2P8ezbZDj97WYrjIOdckalAGzkkqYAfnduOSEiXX4+jiJycqGX8i1tDMAB ZiaWdt3AhNX5f88s2Ci5CCH0RkOjbSwLcUmWcmpGHY+fql5pPSNdqKip037YV4crDeTB y/DYKQSaT7RsIH7Y4eRMyMj0p9g4ZTAVjZDBQvSJpiNbx+Cbl/HZjNFxQ31dKO3z1HPq VWyXlN7sB0Rkukgfof2gM3A3xnP4fMIqcX50fzMJy4znpsa4TKZhQzWqzPRU8oiGzguI naAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=LreumIrE; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: Jassi Brar --- board/socionext/developerbox/developerbox.c | 57 ++++++++++++--------- 1 file changed, 34 insertions(+), 23 deletions(-) diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index b680f77d80..412c811c12 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -56,8 +56,6 @@ struct draminfo { struct draminfo_entry entry[3]; }; -struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; - DECLARE_GLOBAL_DATA_PTR; #define LOAD_OFFSET 0x100 @@ -104,21 +102,44 @@ int ft_board_setup(void *blob, struct bd_info *bd) int dram_init(void) { + struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; + struct draminfo_entry *ent = synquacer_draminfo->entry; + + gd->ram_size = ent[0].size; + gd->ram_base = ent[0].base; + + return 0; +} + +int dram_init_banksize(void) +{ + struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; + struct draminfo_entry *ent = synquacer_draminfo->entry; + int i; + + for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + if (i < synquacer_draminfo->nr_regions) { + debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); + gd->bd->bi_dram[i].start = ent[i].base; + gd->bd->bi_dram[i].size = ent[i].size; + } + } + + return 0; +} + +void build_mem_map(void) +{ + struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; struct draminfo_entry *ent = synquacer_draminfo->entry; struct mm_region *mr; int i, ri; if (synquacer_draminfo->nr_regions < 1) { log_err("Failed to get correct DRAM information\n"); - return -1; + return; } - /* - * U-Boot RAM size must be under the first DRAM region so that it doesn't - * access secure memory which is at the end of the first DRAM region. - */ - gd->ram_size = ent[0].size; - /* Update memory region maps */ for (i = 0; i < synquacer_draminfo->nr_regions; i++) { if (i >= MAX_DDR_REGIONS) @@ -134,24 +155,14 @@ int dram_init(void) mr = &mem_map[DDR_REGION_INDEX(0)]; mem_map[ri].attrs = mr->attrs; } - - return 0; } -int dram_init_banksize(void) +void enable_caches(void) { - struct draminfo_entry *ent = synquacer_draminfo->entry; - int i; - - for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { - if (i < synquacer_draminfo->nr_regions) { - debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); - gd->bd->bi_dram[i].start = ent[i].base; - gd->bd->bi_dram[i].size = ent[i].size; - } - } + build_mem_map(); - return 0; + icache_enable(); + dcache_enable(); } int print_cpuinfo(void)