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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BN3PEPF0000B06A.mail.protection.outlook.com (10.167.243.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7270.0 via Frontend Transport; Tue, 30 Jan 2024 10:48:54 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 30 Jan 2024 04:48:53 -0600 Received: from xhdvineethc40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 30 Jan 2024 04:48:50 -0600 From: Vineeth Karumanchi To: , , , , , , , , , CC: , , , , Subject: [PATCH net-next 1/3] net: macb: queue tie-off or disable during WOL suspend Date: Tue, 30 Jan 2024 16:18:43 +0530 Message-ID: <20240130104845.3995341-2-vineeth.karumanchi@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240130104845.3995341-1-vineeth.karumanchi@amd.com> References: <20240130104845.3995341-1-vineeth.karumanchi@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06A:EE_|MN2PR12MB4287:EE_ X-MS-Office365-Filtering-Correlation-Id: a1e4b64d-d498-46f3-34e8-08dc21810dfd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The RX engine in IP only needs to receive and identify a wake packet through an interrupt. The wake packet is of no further significance; hence, it is not required to be copied into memory. By disabling RX DMA during suspend, we can avoid unnecessary DMA processing of any incoming traffic. During suspend, perform either of the below operations: tie-off/dummy descriptor: Disable unused queues by connecting them to a looped descriptor chain without free slots. queue disable: The newer IP version allows disabling individual queues. Co-developed-by: Harini Katakam Signed-off-by: Harini Katakam Signed-off-by: Vineeth Karumanchi --- drivers/net/ethernet/cadence/macb.h | 7 +++ drivers/net/ethernet/cadence/macb_main.c | 58 +++++++++++++++++++++++- 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index aa5700ac9c00..f68ff163aa18 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -645,6 +645,9 @@ #define GEM_T2OFST_OFFSET 0 /* offset value */ #define GEM_T2OFST_SIZE 7 +/* Bitfields in queue pointer registers */ +#define GEM_RBQP_DISABLE BIT(0) + /* Offset for screener type 2 compare values (T2CMPOFST). * Note the offset is applied after the specified point, * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset @@ -737,6 +740,7 @@ #define MACB_CAPS_HIGH_SPEED 0x02000000 #define MACB_CAPS_CLK_HW_CHG 0x04000000 #define MACB_CAPS_MACB_IS_EMAC 0x08000000 +#define MACB_CAPS_QUEUE_DISABLE 0x00002000 #define MACB_CAPS_FIFO_MODE 0x10000000 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 #define MACB_CAPS_SG_DISABLED 0x40000000 @@ -1254,6 +1258,7 @@ struct macb { u32 (*macb_reg_readl)(struct macb *bp, int offset); void (*macb_reg_writel)(struct macb *bp, int offset, u32 value); + struct macb_dma_desc *rx_ring_tieoff; size_t rx_buffer_size; unsigned int rx_ring_size; @@ -1276,6 +1281,8 @@ struct macb { struct gem_stats gem; } hw_stats; + dma_addr_t rx_ring_tieoff_dma; + struct macb_or_gem_ops macbgem_ops; struct mii_bus *mii_bus; diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 898debfd4db3..47cbea58e6c3 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -2479,6 +2479,12 @@ static void macb_free_consistent(struct macb *bp) bp->macbgem_ops.mog_free_rx_buffers(bp); + if (bp->rx_ring_tieoff) { + dma_free_coherent(&bp->pdev->dev, macb_dma_desc_get_size(bp), + bp->rx_ring_tieoff, bp->rx_ring_tieoff_dma); + bp->rx_ring_tieoff = NULL; + } + for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { kfree(queue->tx_skb); queue->tx_skb = NULL; @@ -2568,6 +2574,16 @@ static int macb_alloc_consistent(struct macb *bp) if (bp->macbgem_ops.mog_alloc_rx_buffers(bp)) goto out_err; + /* Required for tie off descriptor for PM cases */ + if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE)) { + bp->rx_ring_tieoff = dma_alloc_coherent(&bp->pdev->dev, + macb_dma_desc_get_size(bp), + &bp->rx_ring_tieoff_dma, + GFP_KERNEL); + if (!bp->rx_ring_tieoff) + goto out_err; + } + return 0; out_err: @@ -2575,6 +2591,16 @@ static int macb_alloc_consistent(struct macb *bp) return -ENOMEM; } +static void macb_init_tieoff(struct macb *bp) +{ + struct macb_dma_desc *d = bp->rx_ring_tieoff; + /* Setup a wrapping descriptor with no free slots + * (WRAP and USED) to tie off/disable unused RX queues. + */ + macb_set_addr(bp, d, MACB_BIT(RX_WRAP) | MACB_BIT(RX_USED)); + d->ctrl = 0; +} + static void gem_init_rings(struct macb *bp) { struct macb_queue *queue; @@ -2598,6 +2624,8 @@ static void gem_init_rings(struct macb *bp) gem_rx_refill(queue); } + if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE)) + macb_init_tieoff(bp); } static void macb_init_rings(struct macb *bp) @@ -2615,6 +2643,8 @@ static void macb_init_rings(struct macb *bp) bp->queues[0].tx_head = 0; bp->queues[0].tx_tail = 0; desc->ctrl |= MACB_BIT(TX_WRAP); + + macb_init_tieoff(bp); } static void macb_reset_hw(struct macb *bp) @@ -4917,7 +4947,8 @@ static const struct macb_config sama7g5_emac_config = { static const struct macb_config versal_config = { .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | - MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_NEED_TSUCLK, + MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | + MACB_CAPS_QUEUE_DISABLE | MACB_CAPS_NEED_TSUCLK, .dma_burst_length = 16, .clk_init = macb_clk_init, .init = init_reset_optional, @@ -5214,6 +5245,7 @@ static int __maybe_unused macb_suspend(struct device *dev) struct macb_queue *queue; unsigned long flags; unsigned int q; + u32 ctrlmask; int err; if (!device_may_wakeup(&bp->dev->dev)) @@ -5224,6 +5256,30 @@ static int __maybe_unused macb_suspend(struct device *dev) if (bp->wol & MACB_WOL_ENABLED) { spin_lock_irqsave(&bp->lock, flags); + + /* Disable Tx and Rx engines before disabling the queues, + * this is mandatory as per the IP spec sheet + */ + ctrlmask = macb_readl(bp, NCR); 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Advertise wakeup capability in the probe and get the supported modes from the device tree. Re-order MACB_WOL_<> macros for ease of extension. Add ARP support configurable through ethtool, "wolopts" variable in struct macb contains the current WOL options configured through ethtool. For WOL via ARP, ensure the IP address is assigned and report an error otherwise. Co-developed-by: Harini Katakam Signed-off-by: Harini Katakam Signed-off-by: Vineeth Karumanchi --- drivers/net/ethernet/cadence/macb.h | 1 + drivers/net/ethernet/cadence/macb_main.c | 54 ++++++++++++++++++------ 2 files changed, 43 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index f68ff163aa18..db7e95dc56e3 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -1306,6 +1306,7 @@ struct macb { unsigned int jumbo_max_len; u32 wol; + u32 wolopts; /* holds value of rx watermark value for pbuf_rxcutthru register */ u32 rx_watermark; diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 47cbea58e6c3..cbe1a9de692a 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -38,6 +38,7 @@ #include #include #include +#include #include "macb.h" /* This structure is only used for MACB on SiFive FU540 devices */ @@ -84,8 +85,9 @@ struct sifive_fu540_macb_mgmt { #define GEM_MTU_MIN_SIZE ETH_MIN_MTU #define MACB_NETIF_LSO NETIF_F_TSO -#define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0) -#define MACB_WOL_ENABLED (0x1 << 1) +#define MACB_WOL_ENABLED (0x1 << 0) +#define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 1) +#define MACB_WOL_HAS_ARP_PACKET (0x1 << 2) #define HS_SPEED_10000M 4 #define MACB_SERDES_RATE_10G 1 @@ -3276,19 +3278,21 @@ static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) { struct macb *bp = netdev_priv(netdev); - if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) { + if (bp->wol & (MACB_WOL_HAS_MAGIC_PACKET | MACB_WOL_HAS_ARP_PACKET)) phylink_ethtool_get_wol(bp->phylink, wol); + if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) wol->supported |= WAKE_MAGIC; - - if (bp->wol & MACB_WOL_ENABLED) - wol->wolopts |= WAKE_MAGIC; - } + if (bp->wol & MACB_WOL_HAS_ARP_PACKET) + wol->supported |= WAKE_ARP; + /* Pass wolopts to ethtool */ + wol->wolopts = bp->wolopts; } static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) { struct macb *bp = netdev_priv(netdev); int ret; + bp->wolopts = 0; /* Pass the order to phylink layer */ ret = phylink_ethtool_set_wol(bp->phylink, wol); @@ -3298,11 +3302,16 @@ static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) if (!ret || ret != -EOPNOTSUPP) return ret; - if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) || - (wol->wolopts & ~WAKE_MAGIC)) + if (!(bp->wol & (MACB_WOL_HAS_MAGIC_PACKET | MACB_WOL_HAS_ARP_PACKET)) || + (wol->wolopts & ~(WAKE_MAGIC | WAKE_ARP))) return -EOPNOTSUPP; if (wol->wolopts & WAKE_MAGIC) + bp->wolopts |= WAKE_MAGIC; + if (wol->wolopts & WAKE_ARP) + bp->wolopts |= WAKE_ARP; + + if (bp->wolopts) bp->wol |= MACB_WOL_ENABLED; else bp->wol &= ~MACB_WOL_ENABLED; @@ -5086,7 +5095,10 @@ static int macb_probe(struct platform_device *pdev) bp->wol = 0; if (of_property_read_bool(np, "magic-packet")) bp->wol |= MACB_WOL_HAS_MAGIC_PACKET; - device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET); + if (of_property_read_bool(np, "wol-arp-packet")) + bp->wol |= MACB_WOL_HAS_ARP_PACKET; + + device_set_wakeup_capable(&pdev->dev, (bp->wol) ? true : false); bp->usrio = macb_config->usrio; @@ -5243,6 +5255,7 @@ static int __maybe_unused macb_suspend(struct device *dev) struct net_device *netdev = dev_get_drvdata(dev); struct macb *bp = netdev_priv(netdev); struct macb_queue *queue; + struct in_ifaddr *ifa; unsigned long flags; unsigned int q; u32 ctrlmask; @@ -5255,6 +5268,12 @@ static int __maybe_unused macb_suspend(struct device *dev) return 0; if (bp->wol & MACB_WOL_ENABLED) { + /* Check for IP address in WOL ARP mode */ + ifa = rtnl_dereference(bp->dev->ip_ptr->ifa_list); + if ((bp->wolopts & WAKE_ARP) && !ifa) { + netdev_err(netdev, "IP address not assigned\n"); + return -EOPNOTSUPP; + } spin_lock_irqsave(&bp->lock, flags); /* Disable Tx and Rx engines before disabling the queues, @@ -5291,6 +5310,17 @@ static int __maybe_unused macb_suspend(struct device *dev) if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) queue_writel(queue, ISR, -1); } + + ctrlmask = 0; + if (bp->wolopts & WAKE_MAGIC) + ctrlmask = MACB_BIT(MAG); + if (bp->wolopts & WAKE_ARP) { + ctrlmask |= MACB_BIT(ARP); + /* write IP address into register */ + ctrlmask |= cpu_to_be32p(&ifa->ifa_local) + & GENMASK(MACB_IP_SIZE - 1, 0); + } + /* Change interrupt handler and * Enable WoL IRQ on queue 0 */ @@ -5306,7 +5336,7 @@ static int __maybe_unused macb_suspend(struct device *dev) return err; } queue_writel(bp->queues, IER, GEM_BIT(WOL)); - gem_writel(bp, WOL, MACB_BIT(MAG)); + gem_writel(bp, WOL, ctrlmask); } else { err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt, IRQF_SHARED, netdev->name, bp->queues); @@ -5318,7 +5348,7 @@ static int __maybe_unused macb_suspend(struct device *dev) return err; } queue_writel(bp->queues, IER, MACB_BIT(WOL)); - macb_writel(bp, WOL, MACB_BIT(MAG)); + macb_writel(bp, WOL, ctrlmask); } spin_unlock_irqrestore(&bp->lock, flags);