From patchwork Thu Apr 25 17:13:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 792555 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 769AA149E0E; Thu, 25 Apr 2024 17:06:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714064798; cv=none; b=olZA54SnQUW8DHPsecUtzSRUdEkuVvPckHSL8ot/GOSG1xri7zQgk+i7ZoyYOeRFaiwQ36Xk5Qc7JhDFqd+w9/u5eHQuVD4GAE8kPcrirXcK5mYUsiIJRGV+q7S8ggHOK5rAhyuPkwVNjdhzdIw669fQs1jTWm4/lhr8GMqy53k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714064798; c=relaxed/simple; bh=QulXFTzwZLbOFa0Os9JFQ5gDk74pSgjx91XU814wSuQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=gJyQKu7gVW4Q9Pelz8WBodOp0EZpuCbGzgqMm24ZyA6BCaRbq5BTvBnw5hBwuh0/L/Rb5HDr1ltLjR3JwyRNPP4OkzCJG2XEujyDzJLATr0Acl1Y0xMm1vM9bxmob7zmQ0GjH1Fway1CUSI7syUX713HJ4qlgoXO1L6at0YsQXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LtRXTy5V; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LtRXTy5V" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714064797; x=1745600797; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=QulXFTzwZLbOFa0Os9JFQ5gDk74pSgjx91XU814wSuQ=; b=LtRXTy5VrCOfaw1H0desRfef8RVuwhbJ7E0Ts7sxamFRQXfCDgGonUmR 6uHXFFPSs3JZDNccD8tLaiaiSRmCi+ZRrQgfcKoFo07b38MUT+HV+pPZP Aciis2ShRa/iop/UaNN1etklX/ahUm+CJKFdFN4w9n3DiPzkp/wJHiFMx ybSyzUHxxbjvc01XNzbSDIuWvzVYHOSfBb3JaA7fAaLlV876MHZUyfVeZ GYF88+zS833qfPPhLuIiq0UtREmfHpYVKEStNF5XUoHtrdMTkqJdHEEwb /7pVCdlM6hs1/yOChJWlNdRIp8zwLgFqvDSyRCxJh3jtZWh/HKQkER5xp g==; X-CSE-ConnectionGUID: z/x0mv3cT2yL8qEwWImymg== X-CSE-MsgGUID: 5cWzOnZIR2y9bklq1S204Q== X-IronPort-AV: E=McAfee;i="6600,9927,11055"; a="27225301" X-IronPort-AV: E=Sophos;i="6.07,230,1708416000"; d="scan'208";a="27225301" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2024 10:06:35 -0700 X-CSE-ConnectionGUID: eKAQbXk3RQuc9FrhWHJFMw== X-CSE-MsgGUID: emugg8T8RLCSXv1GRCMEVA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,230,1708416000"; d="scan'208";a="25548557" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa006.jf.intel.com with ESMTP; 25 Apr 2024 10:06:34 -0700 From: Ricardo Neri To: "Rafael J. Wysocki" , Zhang Rui , Jean Delvare , Guenter Roeck Cc: Srinivas Pandruvada , Lukasz Luba , Daniel Lezcano , linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v2 1/3] thermal: intel: intel_tcc: Add model checks for temperature registers Date: Thu, 25 Apr 2024 10:13:09 -0700 Message-Id: <20240425171311.19519-2-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240425171311.19519-1-ricardo.neri-calderon@linux.intel.com> References: <20240425171311.19519-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The register MSR_TEMPERATURE_TARGET is not architectural. Its fields may be defined differently for each processor model. TCC_OFFSET is an example of such case. Despite being specified as architectural, the registers IA32_[PACKAGE]_ THERM_STATUS have become model-specific: in recent processors, the digital temperature readout uses bits [23:16] whereas the Intel Software Developer's manual specifies bits [22:16]. Create an array of processor models and their bitmasks for TCC_OFFSET and the digital temperature readout fields. Do not include recent processors. Instead, use the bitmasks of these recent processors as default. Use these model-specific bitmasks when reading TCC_OFFSET or the temperature sensors. Initialize a model-specific data structure during subsys_initcall() to have it ready when thermal drivers are loaded. Expose the new interface intel_tcc_get_offset_mask(). The intel_tcc_cooling driver will use it. Signed-off-by: Ricardo Neri Reviewed-by: Zhang Rui --- Cc: Daniel Lezcano Cc: Lukasz Luba Cc: Srinivas Pandruvada Cc: linux-hwmon@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v6.7+ --- Changes since v1: * Renamed TCC_FAM6_MODEL_TEMP_MASKS as TCC_MODEL_TEMP_MASKS. (Rui) * Renamed get_tcc_offset_mask() as intel_tcc_get_offset_mask(). (Rui) * Do not export intel_tcc_get_temp_mask() as it is no longer used outside intel_tcc.c * Dropped stub functions for digital temperature readout and TCC offset. They are not needed as users select CONFIG_INTEL_TCC. --- drivers/thermal/intel/intel_tcc.c | 177 +++++++++++++++++++++++++++++- include/linux/intel_tcc.h | 1 + 2 files changed, 173 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/intel_tcc.c index 5e8b7f34b395..9943c43c06df 100644 --- a/drivers/thermal/intel/intel_tcc.c +++ b/drivers/thermal/intel/intel_tcc.c @@ -6,8 +6,170 @@ #include #include +#include +#include #include +/** + * struct temp_masks - Bitmasks for temperature readings + * @tcc_offset: TCC offset in MSR_TEMPERATURE_TARGET + * @digital_readout: Digital readout in MSR_IA32_THERM_STATUS + * @pkg_digital_readout: Digital readout in MSR_IA32_PACKAGE_THERM_STATUS + * + * Bitmasks to extract the fields of the MSR_TEMPERATURE and IA32_[PACKAGE]_ + * THERM_STATUS registers for different processor models. + * + * The bitmask of TjMax is not included in this structure. It is always 0xff. + */ +struct temp_masks { + u32 tcc_offset; + u32 digital_readout; + u32 pkg_digital_readout; +}; + +#define TCC_MODEL_TEMP_MASKS(model, _tcc_offset, _digital_readout, \ + _pkg_digital_readout) \ + static const struct temp_masks temp_##model __initconst = { \ + .tcc_offset = _tcc_offset, \ + .digital_readout = _digital_readout, \ + .pkg_digital_readout = _pkg_digital_readout \ + } + +TCC_MODEL_TEMP_MASKS(nehalem, 0, 0x7f, 0x7f); +TCC_MODEL_TEMP_MASKS(haswell_x, 0xf, 0x7f, 0x7f); +TCC_MODEL_TEMP_MASKS(broadwell, 0x3f, 0x7f, 0x7f); +TCC_MODEL_TEMP_MASKS(goldmont, 0x7f, 0x7f, 0x7f); +TCC_MODEL_TEMP_MASKS(tigerlake, 0x3f, 0xff, 0xff); +TCC_MODEL_TEMP_MASKS(sapphirerapids, 0x3f, 0x7f, 0xff); + +/* Use these masks for processors not included in @tcc_cpu_ids. */ +static struct temp_masks intel_tcc_temp_masks __ro_after_init = { + .tcc_offset = 0x7f, + .digital_readout = 0xff, + .pkg_digital_readout = 0xff, +}; + +static const struct x86_cpu_id intel_tcc_cpu_ids[] __initconst = { + X86_MATCH_INTEL_FAM6_MODEL(CORE_YONAH, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(CORE2_MEROM, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(CORE2_MEROM_L, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(CORE2_PENRYN, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(CORE2_DUNNINGTON, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &temp_haswell_x), + X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &temp_haswell_x), + X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &temp_haswell_x), + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &temp_haswell_x), + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &temp_haswell_x), + X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &temp_sapphirerapids), + X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &temp_sapphirerapids), + X86_MATCH_INTEL_FAM6_MODEL(LAKEFIELD, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_MID, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_NP, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &temp_goldmont), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &temp_goldmont), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &temp_goldmont), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &temp_broadwell), + {} +}; + +static int __init intel_tcc_init(void) +{ + const struct x86_cpu_id *id; + + id = x86_match_cpu(intel_tcc_cpu_ids); + if (id) + memcpy(&intel_tcc_temp_masks, (const void *)id->driver_data, + sizeof(intel_tcc_temp_masks)); + + return 0; +} +/* + * Use subsys_initcall to ensure temperature bitmasks are initialized before + * the drivers that use this library. + */ +subsys_initcall(intel_tcc_init); + +/** + * intel_tcc_get_offset_mask() - Returns the bitmask to read TCC offset + * + * Get the model-specific bitmask to extract TCC_OFFSET from the MSR + * TEMPERATURE_TARGET register. If the mask is 0, it means the processor does + * not support TCC offset. + * + * Return: The model-specific bitmask for TCC offset. + */ +u32 intel_tcc_get_offset_mask(void) +{ + return intel_tcc_temp_masks.tcc_offset; +} +EXPORT_SYMBOL_NS(intel_tcc_get_offset_mask, INTEL_TCC); + +/** + * get_temp_mask() - Returns the model-specific bitmask for temperature + * + * @pkg: true: Package Thermal Sensor. false: Core Thermal Sensor. + * + * Get the model-specific bitmask to extract the temperature reading from the + * MSR_IA32_[PACKAGE]_THERM_STATUS register. + * + * Callers must check if the thermal status registers are supported. + * + * Return: The model-specific bitmask for temperature reading + */ +static u32 get_temp_mask(bool pkg) +{ + return pkg ? intel_tcc_temp_masks.pkg_digital_readout : + intel_tcc_temp_masks.digital_readout; +} + /** * intel_tcc_get_tjmax() - returns the default TCC activation Temperature * @cpu: cpu that the MSR should be run on, nagative value means any cpu. @@ -56,7 +218,7 @@ int intel_tcc_get_offset(int cpu) if (err) return err; - return (low >> 24) & 0x3f; + return (low >> 24) & intel_tcc_temp_masks.tcc_offset; } EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, INTEL_TCC); @@ -76,7 +238,10 @@ int intel_tcc_set_offset(int cpu, int offset) u32 low, high; int err; - if (offset < 0 || offset > 0x3f) + if (!intel_tcc_temp_masks.tcc_offset) + return -ENODEV; + + if (offset < 0 || offset > intel_tcc_temp_masks.tcc_offset) return -EINVAL; if (cpu < 0) @@ -90,7 +255,7 @@ int intel_tcc_set_offset(int cpu, int offset) if (low & BIT(31)) return -EPERM; - low &= ~(0x3f << 24); + low &= ~(intel_tcc_temp_masks.tcc_offset << 24); low |= offset << 24; if (cpu < 0) @@ -113,8 +278,8 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, INTEL_TCC); */ int intel_tcc_get_temp(int cpu, int *temp, bool pkg) { - u32 low, high; u32 msr = pkg ? MSR_IA32_PACKAGE_THERM_STATUS : MSR_IA32_THERM_STATUS; + u32 low, high, mask; int tjmax, err; tjmax = intel_tcc_get_tjmax(cpu); @@ -132,7 +297,9 @@ int intel_tcc_get_temp(int cpu, int *temp, bool pkg) if (!(low & BIT(31))) return -ENODATA; - *temp = tjmax - ((low >> 16) & 0x7f); + mask = get_temp_mask(pkg); + + *temp = tjmax - ((low >> 16) & mask); return 0; } diff --git a/include/linux/intel_tcc.h b/include/linux/intel_tcc.h index 8ff8eabb4a98..fa788817acfc 100644 --- a/include/linux/intel_tcc.h +++ b/include/linux/intel_tcc.h @@ -14,5 +14,6 @@ int intel_tcc_get_tjmax(int cpu); int intel_tcc_get_offset(int cpu); int intel_tcc_set_offset(int cpu, int offset); int intel_tcc_get_temp(int cpu, int *temp, bool pkg); +u32 intel_tcc_get_offset_mask(void); #endif /* __INTEL_TCC_H__ */ From patchwork Thu Apr 25 17:13:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 792220 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D14E14D707; Thu, 25 Apr 2024 17:06:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714064798; cv=none; b=WZUmZf+Y8mS9kQCZnX2xwU4uQu/u5Vk0tC8qACEsyL5kvOQPe0IvBZ64t9B9/5YygD7+2I/kGgZ23/RxQEK6F9FgQKCwStVY+4WVfYVLq9QCzeXkePX963HHEMrXraLlcjkT5POz2hYGND8fN6rIhi/kzvBgc26W3myShl5bDMk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714064798; c=relaxed/simple; bh=pAfVKWKU49Dwg4CmC+F0pJ1yRNXxR8Fmblsw2vpiToo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=IeoZVdlkROX6lsqXBjwkNiCizuj2eWFucrk+VzQJrSkGbLwr9GAmV7NLUqut6z674EDFjkHQeejsP7Vx7SfA3hBYFLH4bixZpTAquWPVig9SJKb9zTqjNUhzV57EG5iY6crTRUJORSfyFpWOOc7xTEgpg9GZW/fGenpZgi9Rak4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Jy775qv/; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Jy775qv/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714064797; x=1745600797; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=pAfVKWKU49Dwg4CmC+F0pJ1yRNXxR8Fmblsw2vpiToo=; b=Jy775qv/qNXZR6FbwX7KJmDNwrdXHoo8DEjzeeNaqWizNflaR6+CgEJF goAfgKCVoJV2jYX0ODOlDumCkoihzWfmk25MjN/MvsMvKpCLflPAgirqr IuHBE/9o0X39v35XZE/SUYauDzVoJbsogSX1XB5jOukgNRzg3XKZeQA7b 97DTtFuIa4TOebs4uOxYu+FG9x5g7RlJuktukG4UoJaQxjlmUpOGXWVWD MeKy9HNTdPolv+6rVwU/ox+xTDHqlP8cMRqrF7d3kHpqYvux/VzarrHwE 8FhBo5tvvLGU6K2uyNgSOrWiDZlU+q5y9nxTrgfQdi9dlDxC6/mucUxGk w==; X-CSE-ConnectionGUID: qx/32lGoT0mDMJ7s4IXqyQ== X-CSE-MsgGUID: QFsICatmSBa9pIy9UUsW7A== X-IronPort-AV: E=McAfee;i="6600,9927,11055"; a="27225307" X-IronPort-AV: E=Sophos;i="6.07,230,1708416000"; d="scan'208";a="27225307" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2024 10:06:36 -0700 X-CSE-ConnectionGUID: 1FFUenbyQxav3CT1uCoNFw== X-CSE-MsgGUID: By4Xz9NSRkGw1rS2nLcZzg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,230,1708416000"; d="scan'208";a="25548560" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa006.jf.intel.com with ESMTP; 25 Apr 2024 10:06:35 -0700 From: Ricardo Neri To: "Rafael J. Wysocki" , Zhang Rui , Jean Delvare , Guenter Roeck Cc: Srinivas Pandruvada , Lukasz Luba , Daniel Lezcano , linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v2 2/3] thermal: intel: intel_tcc_cooling: Use a model-specific bitmask for TCC offset Date: Thu, 25 Apr 2024 10:13:10 -0700 Message-Id: <20240425171311.19519-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240425171311.19519-1-ricardo.neri-calderon@linux.intel.com> References: <20240425171311.19519-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The TCC offset field in the register MSR_TEMPERATURE_TARGET is not architectural. The TCC library provides a model-specific bitmask. Use it to determine the maximum TCC offset. Suggested-by: Zhang Rui Signed-off-by: Ricardo Neri Reviewed-by: Zhang Rui --- Cc: Daniel Lezcano Cc: Lukasz Luba Cc: Srinivas Pandruvada Cc: linux-hwmon@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v6.7+ --- Changes since v1: * Used renamed function intel_tcc_get_offset_mask(). --- drivers/thermal/intel/intel_tcc_cooling.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/intel/intel_tcc_cooling.c b/drivers/thermal/intel/intel_tcc_cooling.c index 6c392147e6d1..5bfc2b515c78 100644 --- a/drivers/thermal/intel/intel_tcc_cooling.c +++ b/drivers/thermal/intel/intel_tcc_cooling.c @@ -20,7 +20,7 @@ static struct thermal_cooling_device *tcc_cdev; static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state) { - *state = 0x3f; + *state = intel_tcc_get_offset_mask(); return 0; } From patchwork Thu Apr 25 17:13:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 792554 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D5E214D714; Thu, 25 Apr 2024 17:06:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714064799; cv=none; b=Fm6jPfkFJaXqTelfuG3Rmf4AIOwsd2wfM77XwZeL3g0yGDxEiiXz0vsNQPvM5STY91A2cS3P5ZV10qcuZcha9ImAN+XSLVgG0NSWu4Sm58lWuvkIMzDlVUt6wtddOU9mQXP2Th94RusAvi6VnZ7+iWdzbpm3v/Us1rNar9I7gLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714064799; c=relaxed/simple; bh=viLFxt1UKi1dyqI1aIAAm7qzEwjgBkF02Wj6Ul74LOg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=RoNa5mlnC/5ke5OV8cfeohHFSuz+nxR79A+8JLEI2IeDqG0kIwluF0jNfYHsydeeyz/0Nmntjiw6wBxbFtBwkUd0gqtKENZCoNd8twZcWwgx0KYV8cIgIcS+o7Ps4oTsheHtJY7OCvp/7DXJUTVlv+y7L394xRy5NAc7m7eJVTM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LSxMwlMp; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LSxMwlMp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714064798; x=1745600798; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=viLFxt1UKi1dyqI1aIAAm7qzEwjgBkF02Wj6Ul74LOg=; b=LSxMwlMp3HYil4vH0cQSHLnh32fDysNd+SvG0rc25/7r5mzxMFgjKw0L A1vof1YfE4g11mjW1Se/K8itHmCJ0wmDtuk51k7JDvF/+n0M7FJN0Auug 1J7BeMsS1p9D+/hX8+/V0bOkMVqgZut42XCPZvqgLFvEsjDZjImp89OQo 0zXvurikM0/+5TVPmh1ESrVfXfQ15scWPP8DyHtgRQete0PFwIFHS9Ts2 8ru1kDWEB6A1aj9Ld9Ai68JljDlrbzxGTgU5WNSSQKyC6NI5aIUqS8Xgs RyNyFGPSiHvj+A6gHMhXIwuQ17L16kTbeVFy/M075AWx0Mqu1BgV3oriH A==; X-CSE-ConnectionGUID: aDu/UwrgRriZbG3ggQqQVA== X-CSE-MsgGUID: 2G9wZ0OJQVi9aCapuu/70A== X-IronPort-AV: E=McAfee;i="6600,9927,11055"; a="27225313" X-IronPort-AV: E=Sophos;i="6.07,230,1708416000"; d="scan'208";a="27225313" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2024 10:06:36 -0700 X-CSE-ConnectionGUID: IsLwwQsIR5OEGidYcPIygw== X-CSE-MsgGUID: xGxh8KMGSv+CauYiu7SldA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,230,1708416000"; d="scan'208";a="25548563" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa006.jf.intel.com with ESMTP; 25 Apr 2024 10:06:35 -0700 From: Ricardo Neri To: "Rafael J. Wysocki" , Zhang Rui , Jean Delvare , Guenter Roeck Cc: Srinivas Pandruvada , Lukasz Luba , Daniel Lezcano , linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v2 3/3] hwmon: (coretemp) Extend the bitmask to read temperature to 0xff Date: Thu, 25 Apr 2024 10:13:11 -0700 Message-Id: <20240425171311.19519-4-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240425171311.19519-1-ricardo.neri-calderon@linux.intel.com> References: <20240425171311.19519-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The Intel Software Development manual defines the temperature digital readout as the bits [22:16] of the IA32_[PACKAGE]_THERM_STATUS registers. Bit 23 is specified as reserved. In recent processors, however, the temperature digital readout uses bits [23:16]. In those processors, using the bitmask 0x7f would lead to incorrect readings if the temperature deviates from TjMax by more than 127 degrees Celsius. Although not guaranteed, bit 23 is likely to be 0 in processors from a few generations ago. The temperature reading would still be correct in those processors when using a 0xff bitmask. Model-specific provisions can be made for older processors in which bit 23 is not 0 should the need arise. Signed-off-by: Ricardo Neri --- Cc: Daniel Lezcano Cc: Lukasz Luba Cc: Srinivas Pandruvada Cc: linux-hwmon@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v6.7+ --- Changes since v1: * Corrected wrong sentence in commit message. (Rui) * Removed dependency on INTEL_TCC. (Guenter) --- drivers/hwmon/coretemp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 616bd1a5b864..1b9203b20d70 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -411,7 +411,7 @@ static ssize_t show_temp(struct device *dev, * Return it instead of reporting an error which doesn't * really help at all. */ - tdata->temp = tjmax - ((eax >> 16) & 0x7f) * 1000; + tdata->temp = tjmax - ((eax >> 16) & 0xff) * 1000; tdata->last_updated = jiffies; }