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Thu, 25 Apr 2024 01:24:08 -0500 From: Manikanta Guntupalli To: , , , , , , , , , , , , , , , , , , CC: , , , Manikanta Guntupalli , Krzysztof Kozlowski Subject: [PATCH V3 1/3] dt-bindings: serial: cdns,uart: Add optional reset property Date: Thu, 25 Apr 2024 11:53:56 +0530 Message-ID: <20240425062358.1347684-2-manikanta.guntupalli@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240425062358.1347684-1-manikanta.guntupalli@amd.com> References: <20240425062358.1347684-1-manikanta.guntupalli@amd.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066E7:EE_|DS7PR12MB6237:EE_ X-MS-Office365-Filtering-Correlation-Id: d1bde0dd-7825-4d0d-b369-08dc64f05529 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jMwCIH24GUmXJg4A3WfuxwwpNvcLuAzl0JFDFdupp0uGoSLXpD2p+JGA0IE18V3ZDmvjtoC9dC6PpFhrWDTe9hdphoxwKchzXeeX5Mio3wSmB8QetMviWnODhV51vCquGd9UQICvumeTz0ZUItz2etGAbiVasbyHU7GchWWM+Kj4ggNTkvh4x1QmmpMpvv9FUvsdWkBQ8WQXpOHkBbtQS1l3gQxpCeNpVzzfC2ezNdLjr8J9ezaXFWZGYzbwCKTVdEnoUC48fgY1J606tH+D3bWkKFgS8Yn1/dufpA4/Q/MDGwX0N1Kc0uOZZ81S86dJOr0no1Q76GQrEG9uZgMyMGAf6EogK5bHi8vv3aK2cjn3kZDWZFnsXkXo7fmTsoDxCQvu2HPssFr8MF0h3KKJYO6X4347SRFNka3UtYl1gVNnnSJPCl67JnI4RZrGC/0tFRIueBJtk0mLJ5Z1dl1N+t+/ZOpL0NwbDLUGhj/82+aPivm4SqMu3Cibzih78egSvNTmA1EFyiAIrjX7Vub+ebsW2rQfkqDiKzd3xy8Cza9Vkcn82M5IIINqWWCgP44spvHEQZ6cMA6LG/sGptyzY0nZ58Xy2a3gr+NMXH7aqKlXnfbr4NEXclEEdXrNvuGWCU5FGO6l083iQc/1zMkEhKcSjWsuodPi2BCurqac3c3LCMHGfXMmO8MorRa731WGNxSPc1qrcfHFEecqEdH0KgwIrxh2MhNB/zs/32F0sVvqcf4hRBilHO9SMFy6sXN+00kkR4Q718a6oRGomu9HVTh/Elzf6ZLdE+JWpqPuhlOqil18llxqCvcf8QpwPK8Gi4w9Pzql98ohHghtlBW6HJJFNeXyy6LKIaqUZETYEHdXv/COibgBIUssVJYGhg0rosUYoe8wXCTlL7Je97ubI9HvjowTtsXziTy59WvSrrh+ECQJYFumPvGszIy2D3QkQqs0Eeh3dnxQn/Ua3u3hAUb07Nz/9gUpuTDRpu6+z71fsHIjNa1yOzMSrYnM/Th2iHwTCViWSl/9RELq3M9s1eie+v1PMPgQqPWhEyQGWNvN/RgrGEWo5oeaDX0XoFJQjX7fHeruNiRzfx5ndTYbIlWRUWRI7bS1GkiAOqv1nfL52aYPGURT8B0xBsq5tIa5g4z+1A+Zm5HTHuoMlz52bQrMG1PQhkgj6P0IGq3XrqT2DbjRLXOckTA/TOcCmNIg4BmoYjRfMRa4IGtjPn95yPUgwa0H1tGugpBG/SfurxTrZKK+Bm3f8mvHm9t4LDDNxcOPmtLCL+x1c5td5Ax2E6I52de/f6p7mPF3cEIh6k+/YqzuKZ0RhxPeM46PuaEqiQJ6YJm+1YmWQJZZcy2mcpd5XHHOui0EYA3CEtRVc6/d+McNG+NKtT2LbAYOm7NU X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Signed-off-by: Manikanta Guntupalli Acked-by: Krzysztof Kozlowski --- Changes for V2: Added ack signature. Changes for V3: Corrected typo in subject. --- Documentation/devicetree/bindings/serial/cdns,uart.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml index 2129247d7c81..d7f047b0bf24 100644 --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml @@ -46,6 +46,9 @@ properties: power-domains: maxItems: 1 + resets: + maxItems: 1 + required: - compatible - reg From patchwork Thu Apr 25 06:23:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 792243 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2065.outbound.protection.outlook.com [40.107.93.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A00013F9D2; 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Changes for V3: None. --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 25d20d803230..935504424ec6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -906,6 +906,7 @@ uart0: serial@ff000000 { reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_UART0>; }; uart1: serial@ff010000 { @@ -917,6 +918,7 @@ uart1: serial@ff010000 { reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_UART1>; }; usb0: usb@ff9d0000 { From patchwork Thu Apr 25 06:23:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 792605 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2044.outbound.protection.outlook.com [40.107.93.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C34269953; 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If the uartps node contains the "resets" property, then cdns_uart_startup performs uartps controller non-pulse out of reset and reset in exit path. Signed-off-by: Manikanta Guntupalli --- Changes for V2: Remove check for reset_control_deassert, as reset_control_deassert function internally has NULL check. Changes for V3: None. --- drivers/tty/serial/xilinx_uartps.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c index de3487206bcb..2acfcea403ce 100644 --- a/drivers/tty/serial/xilinx_uartps.c +++ b/drivers/tty/serial/xilinx_uartps.c @@ -25,6 +25,7 @@ #include #include #include +#include #define CDNS_UART_TTY_NAME "ttyPS" #define CDNS_UART_NAME "xuartps" @@ -198,6 +199,7 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); * @gpiod_rts: Pointer to the gpio descriptor * @rs485_tx_started: RS485 tx state * @tx_timer: Timer for tx + * @rstc: Pointer to the reset control */ struct cdns_uart { struct uart_port *port; @@ -211,6 +213,7 @@ struct cdns_uart { struct gpio_desc *gpiod_rts; bool rs485_tx_started; struct hrtimer tx_timer; + struct reset_control *rstc; }; struct cdns_platform_data { u32 quirks; @@ -948,6 +951,10 @@ static int cdns_uart_startup(struct uart_port *port) is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; + ret = reset_control_deassert(cdns_uart->rstc); + if (ret) + return ret; + uart_port_lock_irqsave(port, &flags); /* Disable the TX and RX */ @@ -1721,6 +1728,13 @@ static int cdns_uart_probe(struct platform_device *pdev) dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); } + cdns_uart_data->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); + if (IS_ERR(cdns_uart_data->rstc)) { + rc = PTR_ERR(cdns_uart_data->rstc); + dev_err_probe(&pdev->dev, rc, "Cannot get UART reset\n"); + goto err_out_unregister_driver; + } + rc = clk_prepare_enable(cdns_uart_data->pclk); if (rc) { dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); @@ -1881,6 +1895,7 @@ static void cdns_uart_remove(struct platform_device *pdev) if (console_port == port) console_port = NULL; #endif + reset_control_assert(cdns_uart_data->rstc); if (!--instances) uart_unregister_driver(cdns_uart_data->cdns_uart_driver);