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[209.132.180.131]) by mx.google.com with ESMTPS id z16si10118002edb.420.2019.10.21.08.54.18 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Oct 2019 08:54:19 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-511439-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=GZcWNEF5; spf=pass (google.com: domain of gcc-patches-return-511439-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-511439-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=Azq98fo4sSoYVaH5Y12ofBUS4ZCXg8FFe3nnjPRAG4QBXmDsED MRbg20o3q5L4f4Uxu6pdNO3ceXBYHZTG+Us0dQZKYbPPhCo0tJAB1dFZ4+Vo5t4v Z+L0Efgh5D2w7Vn+7IDsi0Z7yqTXgT14oJhftUeAofW8HjjVMlTqfzvDI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=jfYFp1baV6XdwPlo7xr56yQ4C4g=; b=GZcWNEF5OhvMniZsVio1 JK0bDiT7cAlev2Z60ljj/xSvP48gK1DjIIAzCrm4GlCzpAhtMPcWVomu7U21oZ1s EyTG2HkSx/HsSTQF3czD6XyrQfw0CqVGt5eG6DXFJN2cS5T8Qi3iA6XzUgVMDwC3 aUI+pABMiSbaEGENOLkfCRE= Received: (qmail 128682 invoked by alias); 21 Oct 2019 15:54:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 128561 invoked by uid 89); 21 Oct 2019 15:54:04 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=sk:arm_bor, auditing, RSC, rsc X-HELO: foss.arm.com Received: from Unknown (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 21 Oct 2019 15:54:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B94F52B; Mon, 21 Oct 2019 08:53:53 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.206.225]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 31F183F71F; Mon, 21 Oct 2019 08:53:53 -0700 (PDT) To: "gcc-patches@gcc.gnu.org" From: "Richard Earnshaw (lists)" Subject: [arm] clean up alu+shift patterns Message-ID: Date: Mon, 21 Oct 2019 16:53:52 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 My DImode arithmetic patches introduced a bug on thumb2 where we could generate a register controlled shift into an ALU operation. In fairness the bug was always present, but latent. As part of cleaning this up (and auditing to ensure I've caught them all this time) I've gone through all the shift generating patterns in the MD files and cleaned them up, reducing some duplicate patterns between the arm and thumb2 descriptions where we can now share the same pattern. In some cases we were missing the shift attribute; in most cases I've eliminated an ugly attribute setting using the fact that we normally need separate alternatives for shift immediate and shift reg to simplify the logic. * config/arm/iterators.md (t2_binop0): Fix typo in comment. * config/arm/arm.md (addsi3_carryin_shift): Simplify selection of the type attribute. (subsi3_carryin_shift): Separate into register and constant controlled alternatives. Use shift_amount_operand for operand 4. Set shift attribute and simplify type attribute. (subsi3_carryin_shift_alt): Likewise. (rsbsi3_carryin_shift): Likewise. (rsbsi3_carryin_shift_alt): Likewise. (andsi_not_shiftsi_si): Enable for TARGET_32BIT. Separate constant and register controlled shifts into distinct alternatives. (andsi_not_shiftsi_si_scc_no_reuse): Likewise. (andsi_not_shiftsi_si_scc): Likewise. (arm_cmpsi_negshiftsi_si): Likewise. (not_shiftsi): Remove redundant M constraint from alternative 1. (not_shiftsi_compare0): Likewise. (arm_cmpsi_insn): Remove redundant alternative 2. (cmpsi_shift_swp): Likewise. (sub_shiftsi): Likewise. (sub_shiftsi_compare0_scratch): Likewise. * config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Delete pattern. (thumb2_cmpsi_neg_shiftsi): Likewise. Committed to trunk. R. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 7ef0c16580d..039fdd02479 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1338,9 +1338,7 @@ (define_insn "*addsi3_carryin_shift" (set_attr "arch" "32,a") (set_attr "shift" "3") (set_attr "predicable" "yes") - (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "alu_shift_imm") - (const_string "alu_shift_reg")))] + (set_attr "type" "alu_shift_imm,alu_shift_reg")] ) (define_insn "*addsi3_carryin_clobercc" @@ -1719,71 +1717,68 @@ (define_insn "*subsi3_carryin_const0" ) (define_insn "*subsi3_carryin_shift" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (minus:SI - (match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 1 "s_register_operand" "r,r") (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r") - (match_operand:SI 4 "reg_or_int_operand" "rM")])) + [(match_operand:SI 3 "s_register_operand" "r,r") + (match_operand:SI 4 "shift_amount_operand" "M,r")])) (match_operand:SI 5 "arm_borrow_operation" "")))] "TARGET_32BIT" "sbc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") + (set_attr "arch" "32,a") + (set_attr "shift" "3") (set_attr "predicable" "yes") - (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "alu_shift_imm") - (const_string "alu_shift_reg")))] + (set_attr "type" "alu_shift_imm,alu_shift_reg")] ) (define_insn "*subsi3_carryin_shift_alt" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (minus:SI - (match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 5 "arm_borrow_operation" "")) (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r") - (match_operand:SI 4 "reg_or_int_operand" "rM")])))] + [(match_operand:SI 3 "s_register_operand" "r,r") + (match_operand:SI 4 "shift_amount_operand" "M,r")])))] "TARGET_32BIT" "sbc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") + (set_attr "arch" "32,a") + (set_attr "shift" "3") (set_attr "predicable" "yes") - (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "alu_shift_imm") - (const_string "alu_shift_reg")))] + (set_attr "type" "alu_shift_imm,alu_shift_reg")] ) +;; No RSC in Thumb2 (define_insn "*rsbsi3_carryin_shift" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (minus:SI (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r") - (match_operand:SI 4 "reg_or_int_operand" "rM")]) - (match_operand:SI 1 "s_register_operand" "r")) + [(match_operand:SI 3 "s_register_operand" "r,r") + (match_operand:SI 4 "shift_amount_operand" "M,r")]) + (match_operand:SI 1 "s_register_operand" "r,r")) (match_operand:SI 5 "arm_borrow_operation" "")))] "TARGET_ARM" "rsc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") (set_attr "predicable" "yes") - (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "alu_shift_imm") - (const_string "alu_shift_reg")))] + (set_attr "type" "alu_shift_imm,alu_shift_reg")] ) (define_insn "*rsbsi3_carryin_shift_alt" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (minus:SI (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r") - (match_operand:SI 4 "reg_or_int_operand" "rM")]) + [(match_operand:SI 3 "s_register_operand" "r,r") + (match_operand:SI 4 "shift_amount_operand" "M,r")]) (match_operand:SI 5 "arm_borrow_operation" "")) - (match_operand:SI 1 "s_register_operand" "r")))] + (match_operand:SI 1 "s_register_operand" "r,r")))] "TARGET_ARM" "rsc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") (set_attr "predicable" "yes") - (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "alu_shift_imm") - (const_string "alu_shift_reg")))] + (set_attr "type" "alu_shift_imm,alu_shift_reg")] ) ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. @@ -3268,18 +3263,17 @@ (define_insn "andsi_notsi_si" ) (define_insn "andsi_not_shiftsi_si" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (and:SI (not:SI (match_operator:SI 4 "shift_operator" - [(match_operand:SI 2 "s_register_operand" "r") - (match_operand:SI 3 "arm_rhs_operand" "rM")])) - (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM" + [(match_operand:SI 2 "s_register_operand" "r,r") + (match_operand:SI 3 "shift_amount_operand" "M,r")])) + (match_operand:SI 1 "s_register_operand" "r,r")))] + "TARGET_32BIT" "bic%?\\t%0, %1, %2%S4" [(set_attr "predicable" "yes") (set_attr "shift" "2") - (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") - (const_string "logic_shift_imm") - (const_string "logic_shift_reg")))] + (set_attr "arch" "32,a") + (set_attr "type" "logic_shift_imm,logic_shift_reg")] ) ;; Shifted bics pattern used to set up CC status register and not reusing @@ -3289,19 +3283,18 @@ (define_insn "andsi_not_shiftsi_si_scc_no_reuse" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (and:SI (not:SI (match_operator:SI 0 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_rhs_operand" "rM")])) - (match_operand:SI 3 "s_register_operand" "r")) + [(match_operand:SI 1 "s_register_operand" "r,r") + (match_operand:SI 2 "shift_amount_operand" "M,r")])) + (match_operand:SI 3 "s_register_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=r"))] - "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))" + (clobber (match_scratch:SI 4 "=r,r"))] + "TARGET_32BIT" "bics%?\\t%4, %3, %1%S0" [(set_attr "predicable" "yes") + (set_attr "arch" "32,a") (set_attr "conds" "set") (set_attr "shift" "1") - (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") - (const_string "logic_shift_imm") - (const_string "logic_shift_reg")))] + (set_attr "type" "logic_shift_imm,logic_shift_reg")] ) ;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also @@ -3310,23 +3303,22 @@ (define_insn "andsi_not_shiftsi_si_scc" [(parallel [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (and:SI (not:SI (match_operator:SI 0 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_rhs_operand" "rM")])) - (match_operand:SI 3 "s_register_operand" "r")) + [(match_operand:SI 1 "s_register_operand" "r,r") + (match_operand:SI 2 "shift_amount_operand" "M,r")])) + (match_operand:SI 3 "s_register_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 4 "s_register_operand" "=r") + (set (match_operand:SI 4 "s_register_operand" "=r,r") (and:SI (not:SI (match_op_dup 0 [(match_dup 1) (match_dup 2)])) (match_dup 3)))])] - "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))" + "TARGET_32BIT" "bics%?\\t%4, %3, %1%S0" [(set_attr "predicable" "yes") + (set_attr "arch" "32,a") (set_attr "conds" "set") (set_attr "shift" "1") - (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") - (const_string "logic_shift_imm") - (const_string "logic_shift_reg")))] + (set_attr "type" "logic_shift_imm,logic_shift_reg")] ) (define_insn "*andsi_notsi_si_compare0" @@ -4219,7 +4211,7 @@ (define_insn "*not_shiftsi" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (not:SI (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") - (match_operand:SI 2 "shift_amount_operand" "M,rM")])))] + (match_operand:SI 2 "shift_amount_operand" "M,r")])))] "TARGET_32BIT" "mvn%?\\t%0, %1%S3" [(set_attr "predicable" "yes") @@ -4232,7 +4224,7 @@ (define_insn "*not_shiftsi_compare0" (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") - (match_operand:SI 2 "shift_amount_operand" "M,rM")])) + (match_operand:SI 2 "shift_amount_operand" "M,r")])) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r,r") (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))] @@ -4248,7 +4240,7 @@ (define_insn "*not_shiftsi_compare0_scratch" (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") - (match_operand:SI 2 "shift_amount_operand" "M,rM")])) + (match_operand:SI 2 "shift_amount_operand" "M,r")])) (const_int 0))) (clobber (match_scratch:SI 0 "=r,r"))] "TARGET_32BIT" @@ -7197,43 +7189,43 @@ (define_insn "*arm_cmpsi_insn" (define_insn "*cmpsi_shiftsi" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:SI 0 "s_register_operand" "r,r,r") + (compare:CC (match_operand:SI 0 "s_register_operand" "r,r") (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r,r,r") - (match_operand:SI 2 "shift_amount_operand" "M,r,M")])))] + [(match_operand:SI 1 "s_register_operand" "r,r") + (match_operand:SI 2 "shift_amount_operand" "M,r")])))] "TARGET_32BIT" "cmp\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - (set_attr "arch" "32,a,a") - (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")]) + (set_attr "arch" "32,a") + (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*cmpsi_shiftsi_swp" [(set (reg:CC_SWP CC_REGNUM) (compare:CC_SWP (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r,r,r") - (match_operand:SI 2 "shift_amount_operand" "M,r,M")]) - (match_operand:SI 0 "s_register_operand" "r,r,r")))] + [(match_operand:SI 1 "s_register_operand" "r,r") + (match_operand:SI 2 "shift_amount_operand" "M,r")]) + (match_operand:SI 0 "s_register_operand" "r,r")))] "TARGET_32BIT" "cmp%?\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - (set_attr "arch" "32,a,a") - (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")]) + (set_attr "arch" "32,a") + (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*arm_cmpsi_negshiftsi_si" [(set (reg:CC_Z CC_REGNUM) (compare:CC_Z (neg:SI (match_operator:SI 1 "shift_operator" - [(match_operand:SI 2 "s_register_operand" "r") - (match_operand:SI 3 "reg_or_int_operand" "rM")])) - (match_operand:SI 0 "s_register_operand" "r")))] - "TARGET_ARM" + [(match_operand:SI 2 "s_register_operand" "r,r") + (match_operand:SI 3 "shift_amount_operand" "M,r")])) + (match_operand:SI 0 "s_register_operand" "r,r")))] + "TARGET_32BIT" "cmn%?\\t%0, %2%S1" [(set_attr "conds" "set") - (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") - (const_string "alus_shift_imm") - (const_string "alus_shift_reg"))) + (set_attr "arch" "32,a") + (set_attr "shift" "2") + (set_attr "type" "alus_shift_imm,alus_shift_reg") (set_attr "predicable" "yes")] ) @@ -8945,36 +8937,36 @@ (define_insn "*sub_shiftsi" (define_insn "*sub_shiftsi_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV - (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") + (minus:SI (match_operand:SI 1 "s_register_operand" "r,r") (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r,r,r") - (match_operand:SI 4 "shift_amount_operand" "M,r,M")])) + [(match_operand:SI 3 "s_register_operand" "r,r") + (match_operand:SI 4 "shift_amount_operand" "M,r")])) (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) (match_dup 4)])))] "TARGET_32BIT" "subs%?\\t%0, %1, %3%S2" [(set_attr "conds" "set") (set_attr "shift" "3") - (set_attr "arch" "32,a,a") - (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")]) + (set_attr "arch" "32,a") + (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*sub_shiftsi_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV - (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") + (minus:SI (match_operand:SI 1 "s_register_operand" "r,r") (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r,r,r") - (match_operand:SI 4 "shift_amount_operand" "M,r,M")])) + [(match_operand:SI 3 "s_register_operand" "r,r") + (match_operand:SI 4 "shift_amount_operand" "M,r")])) (const_int 0))) - (clobber (match_scratch:SI 0 "=r,r,r"))] + (clobber (match_scratch:SI 0 "=r,r"))] "TARGET_32BIT" "subs%?\\t%0, %1, %3%S2" [(set_attr "conds" "set") (set_attr "shift" "3") - (set_attr "arch" "32,a,a") - (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")]) + (set_attr "arch" "32,a") + (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn_and_split "*and_scc" diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 5f1c833ad80..4eb203365a6 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -265,7 +265,7 @@ (define_code_iterator PLUSMINUS [plus minus]) (define_code_iterator FCVT [unsigned_float float]) ;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows -;; a stack pointer opoerand. The minus operation is a candidate for an rsub +;; a stack pointer operand. The minus operation is a candidate for an rsub ;; and hence only plus is supported. (define_code_attr t2_binop0 [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")]) diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 8d0b6be9205..7fce50b045b 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -24,20 +24,6 @@ ;; changes made in armv5t as "thumb2". These are considered part ;; the 16-bit Thumb-1 instruction set. -;; Thumb-2 only allows shift by constant on data processing instructions -(define_insn "*thumb_andsi_not_shiftsi_si" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (and:SI (not:SI (match_operator:SI 4 "shift_operator" - [(match_operand:SI 2 "s_register_operand" "r") - (match_operand:SI 3 "const_int_operand" "M")])) - (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_THUMB2" - "bic%?\\t%0, %1, %2%S4" - [(set_attr "predicable" "yes") - (set_attr "shift" "2") - (set_attr "type" "alu_shift_imm")] -) - ;; We use the '0' constraint for operand 1 because reload should ;; be smart enough to generate an appropriate move for the r/r/r case. (define_insn_and_split "*thumb2_smaxsi3" @@ -333,19 +319,6 @@ (define_insn "*thumb2_storewb_pairsi" [(set_attr "type" "store_8")] ) -(define_insn "*thumb2_cmpsi_neg_shiftsi" - [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:SI 0 "s_register_operand" "r") - (neg:SI (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "const_int_operand" "M")]))))] - "TARGET_THUMB2" - "cmn%?\\t%0, %1%S3" - [(set_attr "conds" "set") - (set_attr "shift" "1") - (set_attr "type" "alus_shift_imm")] -) - (define_insn_and_split "*thumb2_mov_scc" [(set (match_operand:SI 0 "s_register_operand" "=l,r") (match_operator:SI 1 "arm_comparison_operator_mode"