From patchwork Thu Mar 26 11:01:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 184851 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1706805ile; Thu, 26 Mar 2020 04:01:49 -0700 (PDT) X-Google-Smtp-Source: ADFU+vs8R8QaRj3PwUnNDbN0qLSL6nlqLx7nNdPO3HHcfa23muXYM0CAo0zZqQhZatW4oPgUQRJE X-Received: by 2002:a17:907:20b4:: with SMTP id pw20mr6788014ejb.113.1585220509501; Thu, 26 Mar 2020 04:01:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1585220509; cv=none; d=google.com; s=arc-20160816; b=zxUyS1FSVowetSgbReBBNP9FOQNm+Lwe/sLkjomwT+kKhnRYFFeTNj+p+BA7Zq3Ylr hlKmgFkOkZiXmo2T+Oh5+FF3Sl2N/JzsEt3SaFMotvzXUmY26MknPj+1eleYpuzjzv1S RQiVkXlwj33l8SqaX2LwrGOpR4cXG455CG4slA7NR9gGEhfc38tOXlDIDXLM4Vh920Vm FF5i4q0zHJVLhO7dygd1cRSj7Fes6OaHNHodhSRr4mPnMs8UY4xzG2i20rz8j7oQYM1S 7Gj4hrbtOUmEj4sTG+ZNevdQMMfC0tD2ZkhZjbfYK3psv4yPwAz5CerK5Ny5tF3125ws JDZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :content-language:mime-version:user-agent:date:message-id:to:subject :from:dmarc-filter:delivered-to; bh=sopxSu3nHVOLQvM5Ol4LvWIEQHUZaTUtr9Bp5yxWqgU=; b=xn6ynoBCJdmFHQvxSNsfvEeynTvrEt9LA36x7QivM+4pbz7IodOfBU1x9m1wecvhiO WfgpN+ZXK6chx7DyG8YYcXsJN0J70hMva+w5GbG70W7IngqJos7AHITa03nzyqOiVz3P mOw3mEu5dZQX1/Q6zLp1qQAoigfz0OYiSiB43dTLMiHxuHwWdeqm+V8amxrIKp3i5vSu eydaEYXZZX3kxvBcgZILVsiOjjkSR8sdWbsd9UAZWfIFzFZxhXB5ce5JT6kb+ZivVsSB IsplHKRtpTqILc+2ZiK6IPJ9DTce0HyLbJWHbf1u3MYkpP8XwBNRoCyBdKUWp91/4jPt 6RfQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom=gcc-patches-bounces@gcc.gnu.org Return-Path: Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id dk16si1277692edb.452.2020.03.26.04.01.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2020 04:01:49 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom=gcc-patches-bounces@gcc.gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 564CA385E01E; Thu, 26 Mar 2020 11:01:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 54E55385E014 for ; Thu, 26 Mar 2020 11:01:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 54E55385E014 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=Richard.Earnshaw@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00F177FA for ; Thu, 26 Mar 2020 04:01:45 -0700 (PDT) Received: from [192.168.1.19] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B1FF3F71F; Thu, 26 Mar 2020 04:01:44 -0700 (PDT) From: "Richard Earnshaw (lists)" Subject: [committed] arm: unified syntax for libgcc when built with -Os [PR94220] To: GCC Patches Message-ID: Date: Thu, 26 Mar 2020 11:01:43 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 Content-Language: en-GB X-Spam-Status: No, score=-29.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The recent patch to convert all thumb1 code in libgcc to unified syntax ommitted the conditional code that is used only when building the library for minimal size. This patch fixes this case. I've also fixed the COND macro so that a single definition is always used that is for unified syntax. This eliminates a warning that is now being seen from the assembler when compiling the ieee fp support code. PR target/94220 * config/arm/lib1funcs.asm (COND): Use a single definition for unified syntax. (aeabi_uidivmod): Unified syntax when optimizing Thumb for size. (aeabi_idivmod): Likewise. (divsi3_skip_div0_test): Likewise. --- libgcc/config/arm/lib1funcs.S | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) /* ------------------------------------------------------------------------ */ /* Bodies of the division and modulo routines. */ -/* ------------------------------------------------------------------------ */ +/* ------------------------------------------------------------------------ */ + .macro ARM_DIV_BODY dividend, divisor, result, curbit #if defined (__ARM_FEATURE_CLZ) && ! defined (__OPTIMIZE_SIZE__) @@ -1136,8 +1137,8 @@ FUNC_START aeabi_uidivmod push {r0, r1, lr} bl LSYM(udivsi3_skip_div0_test) POP {r1, r2, r3} - mul r2, r0 - sub r1, r1, r2 + muls r2, r0 + subs r1, r1, r2 bx r3 # else /* Both the quotient and remainder are calculated simultaneously @@ -1151,7 +1152,7 @@ FUNC_START aeabi_uidivmod ARM_FUNC_START aeabi_uidivmod cmp r1, #0 beq LSYM(Ldiv0) - mov r2, r0 + mov r2, r0 udiv r0, r0, r1 mls r1, r0, r1, r2 RET @@ -1235,29 +1236,29 @@ LSYM(Lover10): beq LSYM(Ldiv0) LSYM(divsi3_skip_div0_test): push { work } - mov work, dividend - eor work, divisor @ Save the sign of the result. + movs work, dividend + eors work, divisor @ Save the sign of the result. mov ip, work - mov curbit, #1 - mov result, #0 + movs curbit, #1 + movs result, #0 cmp divisor, #0 bpl LSYM(Lover10) - neg divisor, divisor @ Loops below use unsigned. + negs divisor, divisor @ Loops below use unsigned. LSYM(Lover10): cmp dividend, #0 bpl LSYM(Lover11) - neg dividend, dividend + negs dividend, dividend LSYM(Lover11): cmp dividend, divisor blo LSYM(Lgot_result) THUMB_DIV_MOD_BODY 0 - mov r0, result + movs r0, result mov work, ip cmp work, #0 bpl LSYM(Lover12) - neg r0, r0 + negs r0, r0 LSYM(Lover12): pop { work } RET @@ -1348,8 +1349,8 @@ FUNC_START aeabi_idivmod push {r0, r1, lr} bl LSYM(divsi3_skip_div0_test) POP {r1, r2, r3} - mul r2, r0 - sub r1, r1, r2 + muls r2, r0 + subs r1, r1, r2 bx r3 # else /* Both the quotient and remainder are calculated simultaneously -- 2.26.0 diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index e8d2158f8d6..a094417e786 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -226,7 +226,6 @@ LSYM(Lend_fde): .endm #define do_push push #define do_pop pop -#define COND(op1, op2, cond) op1 ## op2 ## cond /* Perform an arithmetic operation with a variable shift operand. This requires two instructions and a scratch register on Thumb-2. */ .macro shiftop name, dest, src1, src2, shiftop, shiftreg, tmp @@ -241,12 +240,13 @@ LSYM(Lend_fde): .endm #define do_push stmfd sp!, #define do_pop ldmfd sp!, -#define COND(op1, op2, cond) op1 ## cond ## op2 .macro shiftop name, dest, src1, src2, shiftop, shiftreg, tmp \name \dest, \src1, \src2, \shiftop \shiftreg .endm #endif +#define COND(op1, op2, cond) op1 ## op2 ## cond + #ifdef __ARM_EABI__ .macro ARM_LDIV0 name signed cmp r0, #0 @@ -494,7 +494,8 @@ pc .req r15